Assembly Instructions Chapter 4

4-6 kW UHF Translator Chapter 4, Circuit Descriptions
837B, Rev. 0 4-5
comparator drives the Pin Diode
Attenuator Circuit to maintain the
desired output level, typically +2 dBm.
The other split output connects to J2
the Combined IF Output of the board
that is cabled to the IF Output Jack of
the Tray at J4 (+2 dBm).
Frequency Correction Option
If the Frequency Correction Option
(1227-1528) is purchased, (A13) the IF
Filter/Limiter Board (1109-1001), (A14)
the IF PLL Board (1109-1002), the
(A15) IF Carrier Oven Oscillator Board
(1100-1206), (A4) the VCXO Channel
Oscillator Assembly (1145-1206) and
(A16) an IF Amplifier Board, High Gain
(1197-1126) are part of the System.
4.1.10 (A13) (Optional) IF
Amplifier Board (1197-1126) ;
Appendix D)
A Sample of the amplified and ALC
controlled signal from the IF Filter/ALC
Board is directed to the IF Amplifier
Board, High Gain (1197-1126) where it
is amplified and connected to J2 on
(A13) the IF Filter/Limiter Board (1109-
1001).
4.1.11 (A13) (Optional) IF
Filter/Limiter Board (1109-1001) ;
Appendix D)
The IF is filtered by a SAW Filter, which
passes Visual Carrier and Aural Carrier
only, and amplified before it is split.
The Aural IF Output is not used in this
Tray. The other output of the splitter is
amplified and applied to a Notch Filter.
The Notch Filter is tuned to the Aural
Frequency by C17 and R10 which
reduces or eliminates the Aural IF from
the Visual IF signal. The Visual IF Only
signal then connects to a video detector
circuit which in conjunction with U5
strips the video from the Visual IF
signal. The IF CW Signal is amplified
and buffered before it is connected to
the output of the board at J6. The IF
CW connects to J2 of (A14) the IF PLL
Board (1109-1002).
4.1.12 (A14) (Optional) IF PLL
Board (1109-1002) ; Appendix D)
The IF CW Signal (+3 dBm) on the IF
PLL Board is wired to U1 a Divider IC
which, in conjunction with U2, sets up
one of the reference signals to the
comparator circuit. The other reference
signal is derived from the 50 kHz
reference Input at J4 which is a divided
down 50 kHz sample of the 38.9 MHz
signal generated on (A15) the IF
Carrier Oven Oscillator Board (1100-
1206).
4.1.13 (A15) (Optional) IF Carrier
Oven Oscillator Board (1100-1206)
; Appendix D)
The 38.9 MHz IF Carrier Oven Oscillator
Board is used instead of the 45.75 MHz
IF Carrier Oven Oscillator Board to
minimize the interference between the
generated 45.75 MHz IF and the signal
generated on the (A15) IF Carrier
Oscillator Board. The 38.9 MHz signal
itself is not used, just the divided down
50 kHz reference of the 38.9 MHz
Signal is used. The two reference
signals applied to the IF PLL Board are
compared by U2 and a difference
voltage (AFC) is produced. The
difference voltage (AFC), approximately
-3 VDC, is fed from J3 of the board to
FL2 of (A4) the VCXO Assembly. If the
frequency of the VHF or UHF Input to
the Tray should drift, the ALC voltage
will change to increase or decrease the
output frequency of the VCXO
Assembly which increases or decreases
the L.O. Frequency that maintains the
IF Frequency at the standard 45.75 +
41.25 MHz Frequency. If the frequency
of the Input Signal should drift out of
the capture range of the PLL Circuit,
DS1 the Red LED Unlock Indicator,
located on the IF PLL Board, lights.