Assembly Instructions Chapter 4

4-6 kW UHF Translator Chapter 4, Circuit Descriptions
837B, Rev. 0 4-39
4.7.2 (A2-A1) Variable Gain/Phase
Board (1301549; Appendix D)
The variable gain/phase board provides
the circuits that adjust the phase and
the gain of the RF signal for the
amplifier tray in which it is mounted.
The RF input signal at J1 (+3dBm) is
split, with one output connected to a
detector circuit consisting of C8, CR4,
and U3A. This detected level is then
applied to comparator U3D, which
provides a high output when the input
signal level drops below a threshold set
by R16, R17, and CR5. This high is
applied to the red Input Fault LED DS1,
which lights to indicate an input fault
has occurred. DS1 can be seen through
the hole in the lid on the variable
gain/phase assembly. The high is also
connected to the gate of Q1, which
biases it on and causes its drain to go
low. The low is applied to the pin-diode
attenuator circuit consisting of CR1,
CR2, and CR3. The low to CR3
decreases the current through it and
increases its resistance, decreasing or
completely shutting off the RF applied
through it.
The other output of the RF input signal
from J1 is connected through C1 to a
voltage-controlled, pin-diode attenuator
circuit consisting of diodes CR1, CR2,
and CR3. The diodes are pin diodes in a
pi-type configuration whose resistance
varies inversely with the DC current
flow through them.
As the AGC voltage, attenuator bias,
applied to J5 increases, CR3 is forward
biased even more. This increases the
current flow through it by decreasing
its resistance; the RF signal that flows
through it increases in level. CR1 and
CR2 have less current through them;
this raises their resistance, causing the
RF signal that is applied to them to
decrease in level. The three diodes
form a pi-type attenuator whose
attenuation decreases with the
increasing AGC voltage.
U4 provides amplification,
approximately 8 dB, of the RF signal
before it is connected to the phase-
shifter circuit. The phase-shifter circuit
consists of L1, C16, C17, CR7, and
CR8. L1 is a 90°, 2-way splitter. The
signal at pin 1 of L1 is split and applied
to pins 2 and 4. The signal reflects off
CR7 and CR8 and is passed to pin 3.
The phase shift between pins 1 and 3
changes with the voltage applied across
CR7 and CR8. This voltage is controlled
by an external phase-adjust pot that
connects to J4. The +32 VDC from the
external switching power supply is used
as the reference that is applied to the
phase-control pot. The IC U2 provides
approximately 10 dB of gain at the
output of the phase-shifter circuit that
connects to two class A amplifier
stages, Q2 and Q3, with a total gain of
approximately 20 dB.
The first amplifier stage, Q2, is biased
at a collector current of approximately
100 mA. This current is set by R29,
R30, VR1, and Q2. VR1 forces the
voltage at the collector to stay at 8.9
VDC. This biases on Q2 and draws
enough current through R29 and R30
to keep the collector voltage at 8.9
VDC. The amplified output connects to
the second amplifier Q3. The bias
circuit for Q3 works in a manner similar
to the bias circuit for Q2. VR2 and VR3
maintain a collector voltage of 21 VDC,
while R36 and R37 limit the collector
current to 650 mA.
The output connects to J2 on the
board. A sample of the output is
detected by CR10 and connected to
TP4. A DVM can be connected to TP4 to
give a voltage indication of the RF
output level.
The +32 VDC connects to the board at
J3-3 and is split, with one half
connected to the two, class A amplifier
circuits. The other half of the +32 VDC
input is filtered, isolated by L4 and C13,
and connected to U1. U1 is a +12 VDC
regulator IC that produces the +12