Assembly Instructions Chapter 4

4-6 kW UHF Translator Chapter 4, Circuit Descriptions
837B, Rev. 0 4-14
the input level detector circuit. The
amplified IF is fed to T4; T4 is a step-
up transformer that feeds diode
detector CR14. The positive-going
detected signal is then low-pass filtered
by C49, L18, and C50. This allows only
the video with positive sync to be
applied through emitter follower Q1.
The signal is then connected to
detector CR15 to produce a peak-sync
voltage that is applied to op-amp U9A.
There is a test point at TP3 that
provides a voltage-reference check of
the input level. The detector serves the
dual function of providing a reference
that determines the input IF signal level
to the board and also serves as an
input threshold detector.
The input threshold detector prevents
the automatic level control from
reducing the attenuation of the pin-
diode attenuator to minimum (the
maximum signal) if the IF input to the
board is removed. The ALC, video loss
cutback, and the threshold detector
circuits will only operate when jumper
W3 on jack J6 is in the Auto position,
between pins 1 and 2. Without the
threshold detector, and with the pin-
diode attenuator at minimum, the
signal will overdrive the stages
following this board when it is restored.
As part of the threshold detector
operation, the minimum IF input level
at TP3 is fed through detector CR15 to
op-amp IC U9A pin 2. The reference
voltage for the op-amp is determined
by the voltage divider that consists of
R50 and R51 (off the +12 VDC line).
When the detected input signal level at
U9A, pin 2, falls below this reference
threshold (approximately 10 dB below
the normal input level), the output of
U9A at pin 1 goes to the +12 VDC rail.
This high is connected to the base of
Q2. At this point, Q2 is forward biased
and creates a current path. This path
runs from the -12 VDC line and through
red LED DS1, the input level fault
indicator, which becomes lit, resistor
R54, and transistor Q2 to +12 VDC.
The high from U9A also connects
through diode CR16 to U9B, pin 5,
whose output at pin 7 goes high. The
high connects through range adjust pot
R74 to J20, which connects to the front
panel-mounted power adjust pot. This
high connects to U10A, pin 2, and
causes it to go low at output U10A, pin
1. The low is applied through jumper
W3 on J6 to the pin-diode attenuator
circuit that cuts back the IF level and,
therefore, the output power level, to 0.
When the input signal level increases
above the threshold level, the output
power will raise, as the input level
increases, until normal output power is
reached.
The video input level at TP3 is also fed
to a sync-separator circuit, consisting
of IC U8, CR17, Q3, and associated
components, and then to a comparator
circuit made up of U9C and U9D. The
reference voltage for the comparators
is determined by a voltage divider
consisting of R129, R64, R65, R66, and
R130 (off the -12 VDC line). When the
input signal level to the detector at TP3
falls below this reference threshold,
which acts as a loss-of-sync detector
circuit, the output of U9C and U9D goes
towards the -12 VDC rail and is split,
with one part biasing on transistor Q5.
A current path is then established from
the +12 VDC line through Q5, the
resistors R69 and R137, and the red
LED DS3 (video loss indicator), which is
illuminated. When Q5 is on, it applies a
high to the gates of Q6 and Q7. This
causes them to conduct and apply
video loss fault pull-down outputs to
J18 pins 5 and 2.
The other low output of U9C and U9D is
connected through CR20 to jack J5.
Jumper W2 on J5, in the Cutback
Enable position (between pins 2 and 3),
connects the low to the base of the
forward-biased Q4. If jumper W2 is in
the Disable position, between pins 1
and 2, the auto cutback will not
operate. With Q4 biased on, a level
determined by the setting of cutback