Assembly Instructions Chapter 4

4-6 kW UHF Translator Chapter 4, Circuit Descriptions
837B, Rev. 0 4-12
sample of the delayed video signal is
connected to J2 on the board and can
be used for testing purposes.
The ±12 VDC needed to operate the
board enters the board at J1. The +12
VDC connects to J1-9, which is filtered
by L5 and C11 before it is directed to
the rest of the board. The -12 VDC
connects to J1-6, which is filtered by L6
and C12 before it is directed to the rest
of the board.
4.2.4 (A7) (Optional) IF Carrier
Oven Oscillator Board (1191-1404;
Appendix D)
The IF carrier oven oscillator board
generates the visual IF CW signal at
45.75 MHz for NTSC system "M" usage.
The +12 VDC is applied through jack
J10 to crystal oven HR1, which is
preset to operate at 60° C. The oven
encloses crystal Y1 and stabilizes the
crystal temperature. The crystal is the
principal device that determines the
operating frequency and is the most
sensitive in terms of temperature
stability.
Crystal Y1 operates in an oscillator
circuit consisting of transistor Q1 and
its associated components. Feedback is
provided through a capacitor-voltage
divider, consisting of C5 and C6, that
operates the crystal in a common-base
amplifier configuration using Q1. The
operating frequency of the oscillator
can be adjusted by variable capacitor
C17. The oscillator circuit around Q1
has a separate regulated voltage, 6.8
VDC, which is produced by a
combination of dropping resistor R4
and zener diode VR1. The output of the
oscillator at the collector of Q1 is
capacitively coupled through C8 to the
base of Q2. The small value of C8, 10
pF, keeps the oscillator from being
loaded down by Q2.
Q2 is operated as a common-emitter
amplifier stage whose bias is provided
through R8 from the +12 VDC line. The
output of Q2, at its collector, is split
between two emitter-follower transistor
stages, Q3 and Q4. The output of Q3 is
taken from its emitter through R11 to
establish an approximate 50-ohm
source impedance through C11 to J3,
the main output jack. This 45.75-MHz
signal is at about the +5 dBm power
level. In most systems, this output is
either directed to a visual modulator
board or to some splitting and
amplifying arrangement that distributes
the visual IF carrier for other purposes.
The second output from the collector of
Q2 is fed to the base of Q4, the emitter
follower transistor.
Q4 drives two different output circuits.
One output is directed through voltage
dividers R14 and R15 to jack J2 and is
fed to a frequency counter. While
monitoring J2, the oscillator can be set
exactly on the operating frequency
(45.75 MHz) by adjusting C17. The
output at J2 is at a power level of
approximately -2 dBm, which is
sufficient to drive most frequency
counters. The other output of Q4
connects to prescaler chip U1, which
divides the signal by 15. The output of
U1 is applied to U2, a programmable
divider IC. U2 is programmed through
pins 11 to 20 to divide by 61. This
results in a 50-kHz signal at pin 9 that
is available as an output at J1. The
output of 50 kHz is generally used in
systems where the visual IF carrier
oven oscillator is used as the reference
for a PLL circuit; an example of this is
when the PLL circuit uses the aural IF
synthesizer board and the aural VCO.
The 50-kHz CMOS output at jack J1 is
not capable of achieving enough drive
level for a long coaxial cable length. As
a result, when a long coaxial cable is
needed, the output at jack J5 is
utilized. The push-pull transistor stage
Q5 and Q6, along with emitter resistor
R18, provide a large-load output
capability at J5.