User's Manual

2650 Watt VHF High Band Transmitter Chapter 4, Circuit Descriptions
435B, Rev. 0 4-6
4.1.3 (A6) Delay Equalizer Board
(1227-1204; Appendix D)
The delay equalizer board provides a
delay to the video signal, correction to
the frequency response, and
amplification of the video signal.
The video signal enters the board at J1-2
and is connected to a pi-type, low-pass
filter consisting of C16, L7, and C17. This
filter eliminates any unwanted higher
frequencies from entering the board. The
output of the filter is connected to
amplifier stage U1; the gain is controlled
by R29. The video output of the amplifier
stage is wired to the first of four delay-
equalizing circuits that shape the video
signal to the FCC specification for delay
equalization or to the desired shape
needed for the system. The board has
been factory-adjusted to this FCC
specification and should not be
readjusted without the proper
equipment.
Resistors R7, R12, R17, and R22 adjust
the sharpness of the response curve
while inductors L1, L2, L3, and L4 adjust
the position of the curve. With a delay
equalizer test generator signal or a sine
x/x video test pattern input, the resistors
and inductors can be adjusted, while
monitoring a Tektronix VM700 test
measurement set, until the desired FCC
delay equalization curve or system curve
is attained. The delay-equalized video
signal is connected to J1-4, the video
output of the board. A sample of the
delayed video signal is connected to J2
on the board and can be used for testing
purposes.
The ±12 VDC needed to operate the
board enters the board at J1. The +12
VDC connects to J1-9, which is filtered by
L5 and C11 before it is directed to the
rest of the board. The -12 VDC connects
to J1-6, which is filtered by L6 and C12
before it is directed to the rest of the
board.
4.1.4 (A7) IF Carrier Oven Oscillator
Board (1191-1404; Appendix D)
The IF carrier oven oscillator board
generates the visual IF CW signal at
45.75 MHz for NTSC system "M" usage.
The +12 VDC is applied through jack J10
to crystal oven HR1, which is preset to
operate at 60° C. The oven encloses
crystal Y1 and stabilizes the crystal
temperature. The crystal is the principal
device that determines the operating
frequency and is the most sensitive in
terms of temperature stability.
Crystal Y1 operates in an oscillator circuit
consisting of transistor Q1 and its
associated components. Feedback is
provided through a capacitor-voltage
divider, consisting of C5 and C6, that
connects to the crystal mounted in a
common-base amplifier configuration
using Q1. The operating frequency of the
oscillator can be adjusted by variable
capacitor C17. The oscillator circuit
around Q1 has a separate regulated
voltage, +6.8 VDC, which is produced by
a combination of dropping resistor R4
and zener diode VR1. The output of the
oscillator at the collector of Q1 is
capacitively coupled through C8 to the
base of Q2. The small value of C8, 10 pF,
keeps the oscillator from being loaded
down by Q2.
Q2 is operated as a common-emitter
amplifier stage whose bias is provided
through R8 from the +12 VDC line. The
output of Q2, at its collector, is split
between two emitter-follower transistor
stages, Q3 and Q4. The output of Q3 is
taken from its emitter through R11 to
establish an approximate 50O source
impedance through C11 to J3, the main
output jack. This 45.75 MHz signal is at
about the +5 dBm power level. In most
systems, this output is either directed to
a visual modulator board or to some
splitting and amplifying arrangement that
distributes the visual IF carrier for other
needs. The second output from the
collector of Q2 is fed to the base of Q4,
the emitter follower transistor.