Manual Chapter 3

500-Watt VHF Low Band Transmitter Chapter 3, Circuit Descriptions
325A, Rev. 0 3-23
3.1.9.3 Reflected Level Circuit
A reflected-power sample is applied to J3
of the visual/aural metering board and is
detected by diode detector CR7 and U3B.
The detected output is fed through
reflected calibration pot R39, which can
be adjusted to control the gain of U3C.
The output of U3C connects to J6, pin 7,
which supplies a reflected-power level
output to the front panel meter.
3.1.9.4 Voltages for Circuit Operation
The ±12 VDC is applied to the board at
J5. The +12 VDC is connected to J5, pin
3, and is isolated and filtered by L4 and
C34 before it is connected to the rest of
the board. The +12 VDC also connects to
U5, a 5-VDC regulator that provides the
voltage needed to operate U4. The -12
VDC is applied to J5, pin 1, and is
isolated and filtered by L5 and C35
before it is connected to the rest of the
board.
3.1.10 (A14) Channel Oscillator
Assembly, Dual Oven (1145-1202;
Appendix D)
The channel oscillator assembly contains
(A14-A1) the channel oscillator board
(1145-1201) that generates a stable
frequency-reference signal of
approximately 100 MHz. The channel
oscillator assembly is an enclosure that
provides temperature stability for the
crystal oscillator. An SMA output at jack
J1 and an RF sample at BNC connector
jack J2 are also part of the assembly.
Adjustments can be made through access
holes in the top cover of the assembly.
These adjustments are set at the factory
and should not be tampered with unless
it is absolutely necessary and the proper,
calibrated equipment is available. R1 is
the temperature adjustment; C11 is the
course-frequency adjustment; C9 is the
fine-frequency adjustment; and C6, C18,
L2, and L4 are adjusted for the maximum
output of the frequency as measured at
jack J1.
The +12 VDC for the assembly enters
through FL1 and the circuit-ground
connection is made at E1.
3.1.11 (A4-A13) EEPROM FSK
Identifier Board (1265-1308;
Appendix D)
The FSK identifier board, with EEPROM,
generates a morse code identification call
sign by frequency-shift keying the VCXO
oscillator in the upconverter or by
sending a bias voltage to the IF
attenuator board to amplitude modulate
the aural carrier. This gives the station a
means of automatically repeating its
identification call sign, at a given time
interval, to meet FCC requirements.
The starting circuit is made up of U1B
and U1D, which are connected as a
flip-flop, with gate U1A used as the set
flip-flop. U1A automatically starts the
flip-flop each time U3 completes its
timing cycle. At the start of a cycle, U1B
enables clock U2. U2 applies the clock
pulses that set the speed, which is
adjusted by R2, for when the
identification code is sent to 12-bit binary
counter U4. R2, fully clockwise (CW), is
the fastest pulse train and R2, fully
counter-clockwise (CCW), is the slowest
pulse train. U4 provides binary outputs
that address EEPROM U5.
The scans in U4 will continue until field
effect transistor (FET) Q1 is gated on.
The gate of Q1 is connected to pin 13 on
U4, which is the maximum count used in
the EEPROM, and will provide a reset
pulse each time the binary counter goes
high on pin 13. The reset pulse, when the
drain of Q1 goes low, is applied to the
flip-flop and the timer U3, which
determines the length of time between
the sending of the identification code.
R14 is adjusted to set this time interval.
R14, fully CW, is the longest interval
between identification calls,
approximately eight minutes. R14, fully
CCW, is the shortest interval between the