User's Manual
1 1 7 B 2 0 W at t V H F H igh Band Transla t or UHF/ VHF Re ceive r Tr a y,
w / ( Opt) Freque ncy Cor r e ct ion
Circuit Descript ion
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Com bined I F Signal Path
The L.O. and the RF signals are m ixed in the Mixer St age of the Downconvert er Am plifier Board to
produce t he desired I F difference frequency at - 55 dBm to - 10 dBm in level, depending on t he RF
I nput Level. The Com bined I F Signal is rout ed to ( A11- A1) the I F Filter/ ALC Board ( 1227-1504),
which is m ount ed in ( A11) t he I F Filter/ ALC Enclosure ( 1265-1105). The I F Filt er/ ALC Board
cont ains a Pin Diode Att enuat or circuit which is part of the Autom at ic Level Cont rol ( ALC) t hat
cont rols t he level of t he I F Signal to the t wo st age am plifier I Cs U1 and U2.
The ( Opt ional) (A11- A2) SAW Filter/ Am plifier Board (1035-1211) is also cont ained in the I F
Filt er/ ALC Enclosure. The SAW Filt er/ Am plifier Board connects t o J5 and J6 of t he I F Filter/ ALC
Board if m ore att enuat ion of the Out Of Band product s is needed. I f the SAW Filter/ Am plifier Board
is not needed, a jum per connects t he Com bined I F from J5 to J6 on the I F Filt er/ ALC Board.
The Com bined I F is t hen bandpass filt ered to t he needed 6 MHz I F bandwidt h around the 41.25
MHz + 45.75 MHz Com bined I F signal and am plified by U3 to t he - 41 dBm to + 4 dBm Level before it
is split. One out put is det ect ed by U4 for use as t he ALC reference level t o t he Pin Diode
At tenuator Circuit . The ALC com parat or drives the Pin Diode At t enuator Circuit t o m aintain the
desired out put level, typically + 2 dBm . The other split output connect s t o J2 t he Com bined I F
Out put of t he board that is cabled t o t he I F Output Jack of t he Tray at J4 ( + 2 dBm ) .
Frequency Correct ion Opt ion
I f the Frequency Correction Option (1227- 1528) is purchased, ( A13) t he I F Filter/ Lim it er Board
( 1109- 1001) , ( A14) t he I F PLL Board (1109-1002), t he ( A15) I F Carrier Oven Oscillator Board
( 1100- 1206) , ( A4) t he VCXO Channel Oscillat or Assem bly ( 1145- 1206) and ( A16) an I F Am plifier
Board, High Gain (1197-1126) are part of the System .
A Sam ple of the am plified and ALC cont rolled signal from t he I F Filter/ ALC Board is direct ed t o the
I F Am plifier Board, High Gain ( 1197-1126) where it is am plified and connect ed t o J2 on (A13) the I F
Filt er/ Lim it er Board (1109- 1001) . The I F is filt ered by a SAW Filter, which passes Visual Carrier and
Aural Carrier only, and am plified before it is split. The Aural I F Output is not used in t his Tray. The
ot her out put of the splitt er is am plified and applied t o a Notch Filt er. The Notch Filter is t uned to
the Aural Frequency by C17 and R10 which reduces or elim inates t he Aural I F from t he Visual I F
signal. The Visual I F Only signal then connect s t o a video detect or circuit which in conjunct ion
wit h U5 st rips the video from t he Visual I F signal. The I F CW Signal is am plified and buffered
before it is connect ed to t he out put of t he board at J6. The I F CW connect s t o J2 of ( A14) the I F
PLL Board (1109-1002).
The I F CW Signal (+ 3 dBm ) on the I F PLL Board is wired t o U1 a Divider I C which, in conj unct ion
wit h U2, set s up one of the reference signals to the com parator circuit. The ot her reference signal
is derived from t he 50 kHz reference I nput at J4 which is a divided down 50 kHz sam ple of the 38.9
MHz signal generated on ( A15) the I F Carrier Oven Oscillat or Board ( 1100-1206). The 38.9 MHz I F
Carrier Oven Oscillat or Board is used inst ead of the 45.75 MHz I F Carrier Oven Oscillator Board t o
m inim ize the interference bet ween the generat ed 45.75 MHz I F and the signal generat ed on the
( A15) I F Carrier Oscillator Board. The 38.9 MHz signal itself is not used, j ust the divided down 50
kHz reference of t he 38.9 MHz Signal is used. The t wo reference signals applied t o t he I F PLL
Board are com pared by U2 and a difference voltage (AFC) is produced. The difference volt age
( AFC), approxim at ely - 3 VDC, is fed from J3 of the board to FL2 of ( A4) the VCXO Assem bly. I f
the frequency of t he VHF or UHF I nput t o t he Tray should drift , t he ALC voltage w ill change t o
increase or decrease t he out put frequency of t he VCXO Assem bly which increases or decreases
the L.O. Frequency that m aint ains t he I F Frequency at t he st andard 45.75 + 41.25 MHz
Frequency. I f the frequency of t he I nput Signal should drift out of the capture range of the PLL
Circuit , DS1 t he Red LED Unlock I ndicat or, locat ed on t he I F PLL Board, lights.
Voltages for Operation of t he Tray