Reference Manual

7
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This results in the following mapping of often used peripheral I/Os (LED, PWM, UART1, UART2, SPI
master/slave, I²C master/slave) and analogue inputs, together with resulting wake-up and interrupt
request capabilities
Module
GPIO
ANIO
Port
IRQ
1
Wake-
up
LED
PWM
UART1
UART2
SPI
I2C
SPI
I2C
Pin
Master
Slave
Y1/X7
23
2
C
4
Y
0
2
-
TX
MISO
SDA
MOSI
SDA
Y2/X6
26
5
C
7
Y
3
5
TX
-
MOSI
SCL
MISO
SCL
Y3/X5
25
4
C
6
Y
2
4
RX
TX
SCLK
SDA
SSN
SDA
Y4/X4
24
3
C
5
Y
1
3
-
RX
SSN
SCL
SCLK
SCL
Y6/X2
7
-
A
7
Y
1
5
-
-
-
SCL
SCLK
SCL
Y9/X8
6
-
A
6
Y
-
4
-
-
MOSI
-
SSN
-
Y10/X9
8
-
B
0
Y
2
4
TX
-
-
SDA
MOSI
SDA
Y11/X10
2
-
A
2
Y
2
2
-
TX
SCLK
SDA
MOSI
SDA
Y12/X11
3
-
A
3
Y
3
3
-
RX
MOSI
SCL
SCLK
SCL
Y13/X12
9
-
B
1
Y
3
5
RX
-
-
SCL
MISO
-
Y14/X13
10
-
B
2
Y
0
0
TX
-
-
-
SSN
-
Y15/X14
11
-
B
3
Y
1
1
RX
RX
-
-
SCLK
-
Y16/X15
5
-
A
5
Y
-
4
-
-
MOSI
-
SSN
-
These special purpose debugging and firmware programming signals need to be handled with care.
Specifically, the application circuit must be designed in a way that does not start the processor in
programming/debugging mode. If in-application debugging is desired, avoid using any of the signals
below and route them to a suitable probe connector.
Module
GPIO
SWD
JTAG
Remarks
Pin
Y2/X6
26
PROG_EN
PROG_EN
Low for about one second, then high enables programming mode for 32
seconds.
CAUTION: Make sure that the host board does not inadvertently generate
such a condition!
Y6/X2
7
SWDCLK
TCK
Y7/X1
-
-
-
Active-low system reset
Y9/X8
6
SWDIO
TMS
Y10/X9
8
-
TDI
Y13/X12
9
SWDV
TDO
1
Note: It is possible to select one port per IRQ line. Multiple GPIOs can be configured to raise an interrupt as
long as they belong to different IRQ lines.