Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 92 of 129
C1-Public
2.6.3 SPI interface
2.6.3.1 Guidelines for SPI circuit design
☞ The SPI interface is not available on SARA-R422, SARA-R422S and SARA-R422M8S modules, and
it is not supported by current product versions of SARA-R410M and SARA-R412M modules: the
SPI interface pins should not be driven by any external device.
2.6.4 SDIO interface
2.6.4.1 Guidelines for SDIO circuit design
☞ The SDIO interface is not available on SARA-R422, SARA-R422S and SARA-R422M8S modules,
and it is not supported by current product versions of SARA-R410M and SARA-R412M modules:
the SDIO interface pins should not be driven by any external device.
2.6.5 DDC (I2C) interface
2.6.5.1 Guidelines for DDC (I2C) circuit design
☞ DDC (I2C) interface is not supported by the SARA-R410M-01B product version: the DDC (I2C)
interface pins should not be driven by any external device.
The DDC I2C-bus host interface can be used to communicate with u-blox GNSS receivers and other
external I2C-bus devices as an audio codec.
The SDA and SCL pins of the module are open drain output as per I2C bus specifications [10], and
they have internal pull-up resistors to the V_INT 1.8 V supply rail of the module, so there is no need of
additional pull-up resistors on the external application board.
☞ Capacitance and series resistance must be limited on the bus to match the I2C specifications
(maximum proper rise time for SCL / SDA lines is 1.0 µs): route connections as short as possible.
☞ ESD sensitivity rating of the DDC (I2C) pins is 1 kV (HBM according to JESD22-A114). Higher
protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible points.
☞ If the pins are not used as DDC bus interface, they can be left unconnected.