Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 89 of 129
C1-Public
2.6.2 USB interface
2.6.2.1 Guidelines for USB circuit design
The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single-
ended mode for full speed signaling handshake, as well as in differential mode for high speed signaling
and data transfer.
USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as
required by the USB 2.0 specification [5] are part of the module USB pins driver and do not need to be
externally provided.
The USB interface of SARA-R410M and SARA-R412M modules is enabled only if a valid voltage is
detected by the VUSB_DET input (see the SARA-R4 series data sheet [1]). Neither the USB interface
nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply
voltage and absorbs few microamperes.
Routing the USB pins to a connector, they will be externally accessible on the application device.
According to EMC/ESD requirements of the application, an additional ESD protection device with very
low capacitance should be provided close to accessible point on the line connected to this pin, as
described in Figure 59 and Table 42.
☞ USB interface pins ESD sensitivity rating is 1 kV (HBM according to JESD22-A114F). Higher
protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ultra low capacitance (i.e. < 1 pF) ESD protection (e.g. Littelfuse PESD0402-140 ESD
protection device) on the lines connected to these pins, close to accessible points.
The USB pins of SARA-R410M and SARA-R412M modules can be directly connected to the USB host
application processor without additional ESD protections if they are not externally accessible or
according to EMC/ESD requirements.
D+
D-
GND
29
USB_D+
28
USB_D-
GND
USB DEVICE
CONNECTOR
VBUS
D+
D-
GND
29
USB_D+
28
USB_D-
GND
USB HOST
PROCESSOR
SARA-R410M
SARA-R412M
SARA-R410M
SARA-R412M
VBUS
17
VUSB_DET
17
VUSB_DET
D1 D2 D3
C1
C1
0Ω
Test-Point
0Ω
Test-Point
0Ω
Test-Point
Figure 59: USB Interface application circuits for SARA-R410M and SARA-R412M modules
Reference
Description
Part Number - Manufacturer
C1
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
D1, D2, D3
Very Low Capacitance ESD Protection
PESD0402-140 - Tyco Electronics
Table 42: Components for USB application circuits for SARA-R410M and SARA-R412M modules
☞ If the USB interface is enabled, the module does not enter the low power deep sleep mode: the
external USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module
to let it enter the Power Saving Mode defined in 3GPP Rel.13.
☞ If the USB interface is not used with SARA-R410M and SARA-R412M modules, the USB interface
pins can be left unconnected on the application board, but it is strongly recommended to provide
accessible test points directly connected to the VUSB_DET, USB_D+, and USB_D- pins for FW
upgrade and/or for diagnostic purpose.