Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 84 of 129
C1-Public
2.6 Data communication interfaces
2.6.1 UART interface
2.6.1.1 Guidelines for UART circuit design
Providing the full RS-232 functionality (using the complete V.24 link)
36
If RS-232 compatible signal levels are needed, two different external voltage translators can be used
to provide full RS-232 (9 lines) functionality: e.g. using the Texas Instruments SN74AVC8T245PW for
the translation from 1.8 V to 3.3 V, and the Maxim MAX3237E for the translation from 3.3 V to RS-
232 compatible signal level.
If a 1.8 V Application Processor (DTE) is used and complete RS-232 functionality is required, then the
complete 1.8 V UART of the module (DCE) should be connected to a 1.8 V DTE, as in Figure 51.
TxD
Application Processor
(1.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
SARA-R4 series
(1.8V DCE)
12
TXD
9
DTR
13
RXD
10
RTS
11
CTS
6
DSR
7
RI
8
DCD
GND
0Ω
TP
0Ω
TP
0Ω
TP
0Ω
TP
Figure 51: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE)
If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART of
the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT
output as 1.8 V supply for the voltage translators on the module side, as described in Figure 52.
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
SARA-R4 series
(1.8V DCE)
12
TXD
9
DTR
13
RXD
10
RTS
11
CTS
6
DSR
7
RI
8
DCD
GND
1V8
B1 A1
GND
U1
B3A3
VCCBVCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR3
DIR2 OE
DIR1
VCC
B2 A2
B4A4
DIR4
1V8
B1 A1
GND
U2
B3A3
VCCBVCCA
Unidirectional
Voltage Translator
C3
C4
3V0
DIR1
DIR3 OE
B2 A2
B4A4
DIR4
DIR2
TP
0Ω
TP
0Ω
TP
0Ω
TP
0Ω
TP
Figure 52: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)
Reference
Description
Part Number - Manufacturer
C1, C2, C3, C4
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1, U2
Unidirectional Voltage Translator
SN74AVC4T774
37
- Texas Instruments
Table 38: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)
36
Flow control is not supported by SARA-R410M-01B and SARA-R410M-02B-00 product versions. The RTS input must be set low to
communicate over UART on SARA-R410M-01B product version. The DTR input must be set low to have URCs presented over UART on
SARA-R410M-01B and SARA-R41xM-x2B product versions.
37
Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply