Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 81 of 129
C1-Public
2.5.1.3 Guidelines for single SIM chip connection
A Surface-Mounted SIM chip (M2M UICC Form Factor) must be connected the SIM card interface of
the SARA-R4 series modules as described in Figure 49.
Follow these guidelines to connect the module to a Surface-Mounted SIM chip without SIM presence
detection:
• Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
• Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.
• Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.
• Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.
• Connect the UICC / SIM contact C5 (GND) to ground.
• Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close
to the relative pad of the SIM chip, to prevent digital noise.
• Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM
line, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from
the SIM lines.
• Limit capacitance and series resistance on each SIM signal to match the SIM requirements
(18.7 ns is the maximum allowed rise time on clock line, 1.0 µs is the maximum allowed rise time
on data and reset lines).
41
VSIM
39
SIM_IO
38
SIM_CLK
40
SIM_RST
SIM CHIP
SIM Chip
Bottom View
(contacts side)
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
C2 C3 C5
C4
2
8
3
6
7
1
C1 C5
C2 C6
C3 C7
C4 C8
8
7
6
5
1
2
3
4
SARA-R4 series
C1
U1
Figure 49: Application circuits for the connection to a single Surface-Mounted SIM chip, with SIM detection not implemented
Reference
Description
Part Number - Manufacturer
C1, C2, C3, C4
47 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H470JA01 - Murata
C5
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 - Murata
U1
SIM chip (M2M UICC Form Factor)
Various Manufacturers
Table 36: Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented
2.5.1.4 Guidelines for single SIM card connection with detection
An application circuit for the connection to a single removable SIM card placed in a SIM card holder is
described in Figure 50, where the optional SIM card detection feature is implemented.
Follow these guidelines connecting the module to a SIM connector implementing SIM presence
detection:
• Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
• Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.
• Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.
• Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.
• Connect the UICC / SIM contact C5 (GND) to ground.