Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 61 of 129
C1-Public
2.3.2 Module RESET_N input
2.3.2.1 Guidelines for RESET_N circuit design
The RESET_N input line of the SARA-R410M and SARA-R412M modules is equipped with an internal
pull-up; an external pull-up resistor is not required.
If connecting the RESET_N input to a push button, the pin will be externally accessible on the
application device. According to EMC/ESD requirements of the application, an additional ESD
protection device (e.g. the EPCOS CA05P4S14THSG varistor) should be provided close to accessible
point on the line connected to this pin, as described in Figure 34 and Table 22.
☞ ESD sensitivity rating of the RESET_N pin is 1 kV (HBM according to JESD22-A114). Higher
protection level can be required if the line is externally accessible on the application board, e.g. if
an accessible push button is directly connected to the RESET_N pin, and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point.
An open drain output or open collector output is suitable to drive the RESET_N input from an
application processor, as described in Figure 34.
☞ RESET_N input pin should not be driven high by an external device, as it may cause start up issues.
SARA-R410M
SARA-R412M
18
RESET_N
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
SARA-R410M
SARA-R412M
18
RESET_N
TP
TP
Figure 34: RESET_N application circuits using a push button and an open drain output of an application processor
Reference
Description
Remarks
ESD
CT0402S14AHSG - EPCOS
Varistor array for ESD protection
Table 22: Example of ESD protection component for the RESET_N application circuits
☞ If the external reset function is not required by the customer application, the RESET_N input pin
can be left unconnected to external components, but it is recommended providing direct access
on the application board by means of an accessible test point directly connected to the RESET_N
pin for diagnostic purpose.
2.3.2.2 Guidelines for RESET_N layout design
The RESET_N circuit require careful layout due to the pin function: ensure that the voltage level is well
defined during operation and no transient noise is coupled on this line, otherwise the module might
detect a spurious reset request. It is recommended to keep the connection line to RESET_N pin as
short as possible.