Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 58 of 129
C1-Public
☞ ESD sensitivity rating of the VCC supply pins is 1 kV (HBM according to JESD22-A114). Higher
protection level can be required if the line is externally accessible on the application board, e.g. if
accessible battery connector is directly connected to the supply pins. Higher protection level can
be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to
accessible point.
2.2.1.11 Guidelines for VCC supply layout design
Good connection of the module VCC pins with DC supply source is required for correct RF
performance. Guidelines are summarized in the following list:
• All the available VCC pins must be connected to the DC source
• VCC connection must be as wide as possible and as short as possible
• Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must
be avoided
• VCC connection must be routed through a PCB area separated from RF lines / parts, sensitive
analog signals and sensitive functional units: it is good practice to interpose at least one layer of
PCB ground between the VCC track and other signal routing
• VCC connection must be routed as far as possible from the antenna, in particular if embedded in
the application device: see Figure 32
• Coupling between VCC and digital lines, especially USB, must be avoided.
• The tank bypass capacitor with low ESR for current spikes smoothing described in section
2.2.1.10 should be placed close to the VCC pins. If the main DC source is a switching DC-DC
converter, place the large capacitor close to the DC-DC output and minimize VCC track length.
Otherwise consider using separate capacitors for DC-DC converter and module tank capacitor
• The bypass capacitors in the pF range described in Figure 31 and Table 20 should be placed as
close as possible to the VCC pins, where the VCC line narrows close to the module input pins,
improving the RF noise rejection in the band centered on the Self-Resonant Frequency of the pF
capacitors. This is highly recommended if the application device integrates an internal antenna
• Since VCC input provide the supply to RF Power Amplifiers, voltage ripple at high frequency may
result in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with
switching DC-DC converters, in which case it is better to select the highest operating frequency
for the switcher and add a large L-C filter before connecting to the SARA-R4 series modules in the
worst case
• Shielding of switching DC-DC converter circuit, or at least the use of shielded inductors for the
switching DC-DC converter, may be considered since all switching power supplies may potentially
generate interfering signals as a result of high-frequency high-power switching.
• If VCC is protected by transient voltage suppressor to ensure that the voltage maximum ratings
are not exceeded, place the protecting device along the path from the DC source toward the
module, preferably closer to the DC source (otherwise protection function may be compromised)
SARA
VCC
ANT
Antenna
NOT OK
Antenna
SARA
VCC
ANT
OK
Antenna
SARA
VCC
ANT
NOT OK
Figure 32: VCC line routing guideline for designs integrating an embedded antenna