Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 57 of 129
C1-Public
2.2.1.10 Additional guidelines for VCC supply circuit design
To reduce voltage drops, use a low impedance power source. The series resistance of the supply lines
(connected to the modules’ VCC and GND pins) on the application board and battery pack should also
be considered and minimized: cabling and routing must be as short as possible to minimize losses.
Three pins are allocated to VCC supply connection. Several pins are designated for GND connection.
It is recommended to correctly connect all of them to supply the module minimizing series resistance.
To reduce voltage ripple and noise, improving RF performance especially if the application device
integrates an internal antenna, place the following bypass capacitors near the VCC pins:
• 68 pF capacitor with Self-Resonant Frequency in the 800/900 MHz range (e.g. Murata
GRM1555C1H680J), to filter EMI in the low cellular frequency bands
• 15 pF capacitor with Self-Resonant Frequency in the 1800/1900 MHz range (as Murata
GRM1555C1H150J), to filter EMI in the high cellular frequency bands
• 10 nF capacitor (e.g. Murata GRM155R71C103K), to filter digital logic noise from clocks and data
• 100 nF capacitor (e.g. Murata GRM155R61C104K), to filter digital logic noise from clocks and data
An additional capacitor is recommended to avoid undershoot and overshoot at the start and at the
end of RF transmission:
• 100 µF low ESR capacitor (e.g Kemet T520B107M006ATE015), for SARA-R412M supporting 2G
• 10 µF capacitor (or greater), for the other SARA-R4 series modules that do not support 2G
An additional series ferrite bead is recommended for additional RF noise filtering, in particular if the
application device integrates an internal antenna:
• Ferrite bead specifically designed for EMI suppression in GHz band (e.g. Murata
BLM18EG221SN1), placed as close as possible to the VCC pins of the module, implementing the
circuit described in Figure 31, to filter out EMI in all the cellular bands
C5
GND plane
VCC line
Capacitor with
SRF ~900 MHz
C1 C3 C4
FB1
Ferrite Bead
for GHz noise
C2
C1
GND
C2 C4
SARA-R4 series
52
VCC
53
VCC
51
VCC
3V8
C5
+
FB1
C3
Capacitor with
SRF ~1900 MHz
SARA
Figure 31: Suggested design to reduce ripple / noise on VCC, highly recommended when using an integrated antenna
Reference
Description
Part Number - Manufacturer
C1
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 - Murata
C2
15 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H150JA01 - Murata
C3
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C4
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 - Murata
C5
100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m
T520B107M006ATE015 – Kemet
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
FB1
Chip Ferrite Bead EMI Filter for GHz Band Noise
220 at 100 MHz, 260 at 1 GHz, 2000 mA
BLM18EG221SN1 - Murata
Table 20: Suggested components to reduce ripple / noise on VCC
☞ The necessity of each part depends on the specific design, but it is recommended to provide all
the parts described in Figure 31 / Table 20 if the application device integrates an internal antenna.