Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 56 of 129
C1-Public
2.2.1.9 Guidelines for removing VCC supply
Removing the VCC power can be useful to minimize the current consumption when the SARA-R4
series modules are switched off or when the modules are in deep sleep Power Saving Mode.
In applications in which the module is paired to a host application processor equipped with a RTC, the
module can execute standard PSM procedures, store NAS protocol context in non-volatile memory,
and rely on the host application processor to run its RTC and to trigger wake-up upon need. The
application processor can disconnect the VCC supply source from the module and zero out the
module’s PSM current.
The VCC supply source can be removed using an appropriate low-leakage load switch or p-channel
MOSFET controlled by the application processor as shown in Figure 30, given that the external switch
has provide:
• Ultra low leakage current (for example, less than 1 µA), to minimize the current consumption
• Very low R
DS(ON)
series resistance (for example, less than 50 m), to minimize voltage drops
• Adequate maximum drain current (see the SARA-R4 series data sheet [1] for module current
consumption figures)
C3
GND
C2C1 C4
SARA-R4 series
52
VCC
53
VCC
51
VCC
VCC Supply Source
GND
C5
U1
VOUTVIN
VBIAS
ON
CT
GND
4
V_INT
15
PWR_ON
R1
R2
T1
GPIO
Application
Processor
GPIO
GPIO
+
Figure 30: Example of application circuit for VCC supply removal
Reference
Description
Part Number - Manufacturer
C1
100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m
T520B107M006ATE015 – Kemet
C2
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C3
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C4
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 - Murata
C5
15 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E150JA01 - Murata
R1, R3
47 k Resistor 0402 5% 0.1 W
RC0402JR-0747KL - Yageo Phycomp
R2
10 k Resistor 0402 5% 0.1 W
RC0402JR-0710KL - Yageo Phycomp
T1
NPN BJT Transistor
BC847 - Infineon
U1
Ultra-Low Resistance Load Switch
TPS22967 - Texas Instruments
Table 19: Components for VCC supply removal application circuit
☞ It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4 series
normal operations: the VCC supply can be removed only after V_INT goes low, indicating that the
module has entered Deep-Sleep Power Saving Mode or Power-Off Mode.
☞ See the section 2.2.1.10, and in particular Figure 31 / Table 20, for the parts recommended to be
provided if the application device integrates an internal antenna.