Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 50 of 129
C1-Public
Figure 25 and the components listed in Table 15 show an example of a low cost power supply circuit,
where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified
highest peak / pulse current, with an appropriate power handling capability. The regulator described
in this example supports a limited input voltage range and it includes internal circuitry for current and
thermal protection.
It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly
below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit
described in Figure 25 and Table 15). This reduces the power on the linear regulator and improves the
whole thermal design of the supply circuit.
5V
C1
IN
OUT
ADJ
GND
1
2
4
5
3
R1
R2
U1
EN
SARA-R4 series
52
VCC
53
VCC
51
VCC
GND
C2
C3 C4 C5 C6
Figure 25: Example of low cost VCC supply circuit for SARA-R4 series modules, using an LDO linear regulator
Reference
Description
Part Number - Manufacturer
C1
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
Generic manufacturer
C2
100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m
T520B107M006ATE015 – Kemet
C3
100 nF Capacitor Ceramic X7R 16 V
GRM155R71C104KA01 - Murata
C4
10 nF Capacitor Ceramic X7R 16 V
GRM155R71C103KA01 - Murata
C5
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1E680JA01 - Murata
C6
15 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1E150JA01 - Murata
R1
27 k Resistor 0402 5% 0.1 W
Generic manufacturer
R2
4.7 k Resistor 0402 5% 0.1 W
Generic manufacturer
U1
LDO Linear Regulator ADJ 3.0 A
LP38501ATJ-ADJ/NOPB - Texas Instrument
Table 15: Suggested components for low cost VCC supply circuit for SARA-R4 modules, using an LDO linear regulator
☞ See the section 2.2.1.10, and in particular Figure 31 / Table 20, for the parts recommended to be
provided if the application device integrates an internal antenna.