Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 42 of 129
C1-Public
2 Design-in
2.1 Overview
For an optimal integration of the SARA-R4 series modules in the final application board, follow the
design guidelines stated in this section.
Every application circuit must be suitably designed to guarantee the correct functionality of the
relative interface, but a number of points require particular attention during the design of the
application device.
The following list provides a rank of importance in the application design, starting from the highest
relevance:
1. Module antenna(s) connection: ANT, ANT_GNSS, and ANT_DET pins.
Cellular antenna circuit directly affects the RF compliance of the device integrating a SARA-R4
series module with applicable certification schemes. Follow the suggestions provided in the
relative section 2.4 for the schematic and layout design.
2. Module supply: VCC and GND pins.
The supply circuit affects the RF compliance of the device integrating a SARA-R4 series module
with the applicable required certification schemes as well as the antenna circuit design. Very
carefully follow the suggestions provided in the relative section 2.2.1 for the schematic and layout
design.
3. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST pins.
Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling.
Carefully follow the suggestions provided in relative section 2.5 for schematic and layout design.
4. System functions: RESET_N and PWR_ON / PWR_CTRL pins.
Accurate design is required to guarantee that the voltage level is well defined during operation.
Carefully follow the suggestions provided in relative section 2.3 for schematic and layout design.
5. USB interface: USB_D+, USB_D- and VUSB_DET / USB_5V0, USB_3V3 pins.
Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully
follow the suggestions provided in the relative section 2.6.2 for the schematic and layout design.
6. Other digital interfaces: UART, SPI, SDIO, I2C, I2S, GPIOs, GNSS PIOs and reserved pins.
Accurate design is required to guarantee correct functionality and reduce the risk of digital data
frequency harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.2, 2.6.3,
2.6.4, 2.6.5, 2.7, 2.8 and 2.10 for the schematic and layout design.
7. Other supplies: V_INT generic digital interfaces supply.
Accurate design is required to guarantee correct functionality. Follow the suggestions provided in
the corresponding section 2.2.2 for the schematic and layout design.
☞ It is recommended to follow the specific design guidelines provided by each manufacturer of any
external part selected for the application board integrating the u-blox cellular modules.