Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 System description Page 29 of 129
C1-Public
1.6 System function interfaces
1.6.1 Module power-on
When the SARA-R4 series modules are in the not-powered mode (i.e. the VCC module supply is not
applied), they can be switched on as follows:
• Rising edge on the VCC input pins to a valid voltage level, and then a low logic level needs to be set
at the PWR_ON / PWR_CTRL input pin for a valid time.
When the SARA-R4 series modules are in the power-off mode (i.e. switched off) or in the Power Saving
Mode (PSM), with a valid VCC supply applied, they can be switched on as follows:
• Low pulse on the PWR_ON / PWR_CTRL pin for a valid time period
The PWR_ON / PWR_CTRL input pin is equipped with an internal active pull-up resistor. Detailed
characteristics with voltages and timings are described in the SARA-R4 series data sheet [1].
Figure 14 shows the module switch-on sequence from the not-powered mode, with following phases:
• The external power supply is applied to the VCC module pins
• The PWR_ON / PWR_CTRL pin is held low for a valid time
• All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT).
• The internal reset signal is held low: the baseband core and all digital pins are held in reset state.
When the internal reset signal is released, any digital pin is set in the correct sequence from the
reset state to the default operational configured state. The duration of this phase differs within
generic digital interfaces and USB interface due to host / device enumeration timings.
• The module is fully ready to operate after all interfaces are configured.
VCC
PWR_ON / PWR_CTRL
RESET_N
V_INT
Internal Reset
GPIO
System State
BB Pads State Operational
OFF
ON
Internal Reset → Operational
Tristate / Floating
Internal Reset
Start of interface
configuration
Module interfaces
are configured
Start-up
event
Figure 14: SARA-R4 series switch-on sequence description
☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor:
o the V_INT pin, to sense the start of the SARA-R4 series module switch-on sequence
o the GPIO pin configured to provide the module operating status indication (see SARA-R4 series
commands manual [2], +UGPIOC AT command), to sense when the module is ready to operate
☞ Before the switch-on of the generic digital interface supply (V_INT) of the module, no voltage
driven by an external application should be applied to any generic digital interface of the module.
☞ Before the SARA-R4 series module is fully ready to operate, the host application processor should
not send any AT command over AT communication interfaces (USB, UART) of the module.
☞ The duration of the SARA-R4 series modules’ switch-on routine can largely vary depending on the
application / network settings and the concurrent module activities.
⚠ An abrupt removal of the VCC supply, or forcing an abrupt emergency reset / switch off by
asserting the RESET_N / PWR_CTRL input, once the boot of SARA-R4 series modules has been
triggered may lead to an unrecoverable faulty state!