Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 System description Page 14 of 129
C1-Public
1.3 Pin-out
Table 3 lists the pin-out of the SARA-R4 series modules, with pins grouped by function.
Function
Pin Name
Pin No
I/O
Description
Remarks
Power
VCC
51,52,53
I
Module supply
input
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.
GND
1,3,5,14,
20-22,30,
32,43,50,
54,55,
57-61,
63-96
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
V_INT
4
O
Generic digital
interfaces supply
output
V_INT = 1.8 V (typical) generated by internal regulator when
the module is switched on, outside the low power PSM deep
sleep mode.
Test-Point for diagnostic / FW update strongly recommended.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
System
PWR_ON
11
15
I
Power-on / -off
input
Internal 200 k pull-up resistor.
Test-Point for diagnostic / FW update strongly recommended.
See section 1.6.1 and 1.6.2 for functional description.
See section 2.3.1 for external circuit design-in.
PWR_CTRL
12
15
I
Power-on / -off /
Reset input
Internal pull-up resistor.
Test-Point for diagnostic / FW update strongly recommended.
See section 1.6.1, 1.6.2 and 1.6.3 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
11
18
I
Reset input
Internal 37 k pull-up resistor.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
Antenna
ANT
56
I/O
Cellular antenna
RF input/output
RF input/output for external Cellular antenna.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and application
device compliance with required certification schemes.
See section 1.7.1 for functional description / requirements.
See section 2.4 for external circuit design-in.
ANT_GNSS
13
31
I
GNSS antenna RF
input
RF input for external GNSS antenna.
50 nominal characteristic impedance.
See section 1.7.2 for functional description / requirements.
See section 2.4.3 for external circuit design-in.
ANT_DET
62
I
Antenna detection
ADC for antenna presence detection function
See section 1.7.3 for functional description.
See section 2.4.5 for external circuit design-in.
11
SARA-R410M, SARA-R412M modules only
12
SARA-R422, SARA-R422S, SARA-R422M8S modules only
13
SARA-R422M8S modules only