Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC current consumption in 2G connected mode
- 1.5.1.4 VCC current consumption in ultra low power deep sleep mode
- 1.5.1.5 VCC current consumption in low power idle mode
- 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 GNSS peripheral input output
- 1.13 Reserved pins (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R4x2
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Additional guidelines for VCC supply circuit design
- 2.2.1.11 Guidelines for VCC supply layout design
- 2.2.1.12 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio
- 2.8 General Purpose Input/Output
- 2.9 GNSS peripheral input output
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 Module footprint and paste mask
- 2.13 Thermal guidelines
- 2.14 Schematic for SARA-R4 series module integration
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science, Economic Development Canada notice
- 4.4 European Conformance CE mark
- 4.5 National Communication Commission Taiwan
- 4.6 ANATEL Brazil
- 4.7 Australian Conformance
- 4.8 GITEKI Japan
- 4.9 KC South Korea
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documentation
- Revision history
- Contact
SARA-R4 series - System integration manual
UBX-16029218 - R20 Design-in Page 101 of 129
C1-Public
2.15 Design-in checklist
This section provides a design-in checklist.
2.15.1 Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at VCC pin within the operating range limits.
DC supply must be capable of supporting the highest peak / pulse current consumption values
and the maximum averaged current consumption values in connected mode, as specified in
the SARA-R4 series data sheet [1].
VCC voltage supply should be clean, with very low ripple/noise: provide the suggested bypass
capacitors, in particular if the application device integrates an internal antenna.
Do not apply loads which might exceed the limit for maximum available current from V_INT
supply.
Check that voltage level of any connected pin does not exceed the relative operating range.
Provide accessible test points directly connected to the RESET_N pin for diagnostic purposes.
Capacitance and series resistance must be limited on each SIM signal to match the SIM
specifications.
Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if
accessible.
Check UART signals direction, as the modules’ signal names follow the ITU-T V.24
recommendation [6].
Capacitance and series resistance must be limited on each high speed line of the USB
interface.
It is strongly recommended to provide accessible test points directly connected to the V_INT,
PWR_ON / PWR_CTRL, VUSB_DET / USB_5V0, USB_3V3, USB_D+, USB_D-, and RSVD #33
pins for diagnostic and/or FW update purposes.
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k
resistor on the board in series to the GPIO when those are used to drive LEDs.
Provide adequate precautions for EMC / ESD immunity as required on the application board.
Do not apply voltage to any generic digital interface pin of SARA-R4 series modules before the
switch-on of the generic digital interface supply source (V_INT).
All unused pins can be left unconnected.
2.15.2 Layout checklist
The following are the most important points for a simple layout check:
Check 50 nominal characteristic impedance of the RF transmission line connected to the
ANT port (antenna RF interface).
Ensure no coupling occurs between the RF interface and noisy or sensitive signals (SIM
signals, high-speed digital lines such as USB, and other data lines).
Optimize placement for minimum length of RF line.
Check the footprint and paste mask designed for SARA-R4 series module as illustrated in
section 2.12.
VCC line should be enough wide and as short as possible.
Route VCC supply line away from RF line / part (refer to Figure 32) and other sensitive analog
lines / parts.