Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 90 of 123
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2.13.2 Layout checklist
The following are the most important points for a simple layout check:
Check 50 nominal characteristic impedance of the RF transmission line connected to the ANT
port (cellular antenna RF interface).
Check cellular antenna trace design for regulatory compliance perspective (see section 4.2.3 for
FCC United States, section 4.3.2 for ISED Canada, and related section 2.4.2.3)
For SARA-R510M8S, check 50 nominal characteristic impedance of the RF transmission line
connected to the ANT_GNSS port (GNSS antenna RF interface).
Ensure no coupling occurs between the RF interfaces and noisy or sensitive signals (like SIM
signals and high-speed digital lines).
Optimize placement for minimum length of RF lines.
Check the footprint and paste mask designed for SARA-R5 series module as illustrated in
section 2.11.
VCC line should be enough wide and as short as possible.
Route VCC supply line away from RF lines / parts (refer to Figure 27) and other sensitive analog
lines / parts.
The VCC bypass capacitors in the picoFarad range should be placed as close as possible to the
VCC pins, in particular if the application device integrates an internal antenna.
Ensure an optimal grounding connecting each GND pin with application board solid ground layer.
Use as many vias as possible to connect the ground planes on multilayer application board,
providing a dense line of vias at the edges of each ground area, in particular along RF and high
speed lines.
Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal
integrity.
USB_D+ / USB_D- traces should meet the characteristic impedance requirement (90 differential
and 30 common mode) and should not be routed close to any RF line / part.
2.13.3 Antennas checklist
Antenna termination should provide 50 characteristic impedance with V.S.W.R at least less
than 3:1 (recommended 2:1) on operating bands in deployment geographical area.
Follow the recommendations of the antenna producer for correct antenna installation and
deployment (PCB layout and matching circuitry).
Ensure compliance with any regulatory agency RF radiation requirement, as reported in section
4.2.2 for FCC United States, in section 4.3.1 for ISED Canada, and in section 4.4 for RED Europe.
Ensure high isolation between the cellular antenna and any other antennas or transmitters
present on the end device.
For SARA-R510M8S, ensure high isolation between the cellular antenna and the GNSS antenna
(see also section 1.7.4)