Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 88 of 123
Confidential
2.12 Schematic for SARA-R5 series module integration
Figure 68 is an example of a schematic diagram where a SARA-R5 series product is integrated into an
application board using most of the available interfaces and functions of the module.
3V8
GND
10uF 10nF
SARA-R5 series
52 VCC
53 VCC
51 VCC
68pF
RSVD2
18 RESET_N
Application
processor
Open
drain
output
15 PWR_ON
Open
drain
output
TP
TP
47pF
SIM CARD
HOLDER
VCC (C1)
VPP (C6)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
47pF47pF 100nF
41VSIM
39SIM_IO
38SIM_CLK
40SIM_RST
47pF
SW1
SW2
4V_INT
42GPIO5
470k
ESD ESD ESD ESD ESD ESD
1k
TP
V_INT
62
ANT_DET
10k
27pF
ESD
68nH
56
Connector
Cellular
antenna
33pF
ANT
29
USB_D+
28
USB_D-
17
VUSB_DET
TP
TP
TP
39nH
15pF
15pF100nF
24GPIO3
V_INT
B1 A1
GND
B2 A2
VCCB VCCA
SN74AVC2T245
voltage translator
100nF
100nF
3V0
TXD1
4.7k
IN
OUT
LDO regulator
SHDN
4.7k
3V8 3V0
23GPIO2
V_INT
SDA_A
SDA_B
GND
SCL_A
SCL_B
VCCA
VCCB
TCA9406
I2C voltage translator
100nF
100nF
100nF
47k
SDA2
SCL2
VCC
DIR1
DIR2OE
OE
GND
EXTINT0GPIO4 25
u-blox GNSS
3.0 V receiver
26SDA
27SCL
Not supported by SARA-R510M8S modules
EXT_INT
33
3V8
Network
indicator
16
GPIO1
19GPIO6
SDIO_CMD
SDIO_D0
SDIO_D3
SDIO_D1
46
47
48
49
SDIO_D2
SDIO_CLK
44
45
36I2S_CLK / SPI_CLK
34I2S_WA / SPI_MOSI
35I2S_TXD / SPI_CS
37I2S_RXD / SPI_MISO
12
TXD
13
RXD
8
DCD
10
RTS
11
CTS
9
DTR
6
DSR
7
RI
TP
TP
TXD
RXD
DCD
RTS
CTS
DTR
DSR
RI
1.8 V DTE
GND GND
0Ω
0Ω
TP
TP
0Ω
0Ω
ANT_GNSS
31
GNSS
antenna
Not supported by SARA-R510S modules
SAW
LNA
Figure 68: Example of schematic diagram to integrate a SARA-R5 series module using all available interfaces