Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 86 of 123
Confidential
☞ Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor
on the board in series to the GPIO of SARA-R5 series modules.
☞ Do not apply voltage to any GPIO of the module before the switch-on of the GPIOs supply (V_INT),
to avoid latch-up of circuits and allow a clean module boot. If the external signals connected to the
module cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI
SN74CB3Q16244, TS5A3159, TS5A63157) between the two-circuit connections and set to high
impedance before V_INT switch-on.
☞ ESD sensitivity rating of the GPIO pins is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level could be required if the lines are externally accessible and it can be achieved
by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible
points.
☞ If the GPIO pins are not used, they can be left unconnected on the application board.
2.8.2 Guidelines for general purpose input/output layout design
The general purpose input / output pins are generally not critical for layout.
2.9 Reserved pin (RSVD)
SARA-R5 series modules have a pin reserved for future use, marked as RSVD. This pin is to be left
unconnected on the application board.
2.10 Module placement
An optimized placement allows minimum RF lines’ length and closer path from DC source for VCC.
Make sure that the module, analog parts and RF circuits are clearly separated from any possible
source of radiated energy. In particular, digital circuits can radiate digital frequency harmonics, which
can produce electro-magnetic interference that affects the module, analog parts and RF circuits’
performance. Implement suitable countermeasures to avoid any possible electro-magnetic
compatibility issue.
Make sure that the module is placed in order to keep the antenna (or antennas, for SARA-R510M8S)
as far as possible from VCC supply line and related parts (refer to Figure 27), from high speed digital
lines (as USB) and from any possible noise source.
Provide enough clearance between the module and any external part: clearance of at least 0.4 mm per
side is recommended to let suitable mounting of the parts.
☞ The heat dissipation during continuous transmission at maximum power can raise the
temperature of the application base-board below the SARA-R5 series modules: avoid placing
temperature sensitive devices close to the module.