Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 84 of 123
Confidential
Connection with u-blox 3.0 V GNSS receivers
☞ Communication with an external GNSS receiver is not supported by SARA-R510M8S modules.
Figure 65 shows an application circuit for connecting the cellular module to a u-blox 3.0 V GNSS
receiver:
As the SDA and SCL pins of the cellular module are not tolerant up to 3.0 V, the connection to the
related I2C pins of the u-blox 3.0 V GNSS receiver must be provided using a suitable I2C-bus
bidirectional voltage translator (e.g. TI TCA9406, which additionally provides the partial power
down feature so that the GNSS 3.0 V supply can be ramped up before the V_INT 1.8 V cellular
supply). External pull-up resistors are not needed on the cellular module side, as they are already
integrated in the cellular module.
The GPIO2 is connected to the active-high enable pin of the voltage regulator that supplies the
u-blox 3.0 V GNSS receiver providing the “GNSS supply enable” function. A pull-down resistor is
provided to avoid a switch-on of the positioning receiver when the cellular module is switched off
or in the reset state.
The GPIO3 and GPIO4 pins are connected respectively to the TXD1 and EXTINT0 pins of the u-blox
3.0 V GNSS receiver providing “GNSS data ready” and “GNSS RTC sharing” functions, using a
suitable unidirectional general purpose voltage translator (e.g. TI SN74AVC2T245, which
additionally provides the partial power down feature so that the 3.0 V GNSS supply can be also
ramped up before the V_INT 1.8 V cellular supply).
For additional guidelines regarding the design of applications with u-blox 3.0 V GNSS receivers, see
the hardware integration manuals of the u-blox GNSS receivers.
u-blox GNSS
3.0 V receiver
24
GPIO3
1V8
B1 A1
GND
U3
B2A2
VCCBVCCA
Unidirectional
voltage translator
C4
C5
3V0
TXD1
R1
INOUT
LDO regulator
SHDN
R2
VMAIN3V0
U1
23
GPIO2
26
SDA
27
SCL
1V8
SDA_A SDA_B
GND
U2
SCL_ASCL_B
VCCA
VCCB
I2C-bus bidirectional
voltage translator
4
V_INT
C1
C2 C3
R3
SDA2
SCL2
VCC
DIR1
DIR2 OE
OE
GNSS data ready
GNSS supply enable
GND
SARA-R500S / SARA-R510S
25
GPIO4EXTINT0
GNSS RTC sharing
Figure 65: Application circuit for connecting SARA-R500S/SARA-R510S modules to a u-blox 3.0 V GNSS receiver
Reference
Description
Part number - Manufacturer
R1, R2
4.7 kΩ resistor 0402 5% 0.1 W
Generic manufacturer
R3
47 kΩ resistor 0402 5% 0.1 W
Generic manufacturer
C2, C3, C4, C5
100 nF capacitor ceramic X5R 0402 10% 10V
GCM155R71C104KA55 - Murata
U1, C1
Voltage regulator for GNSS receiver and
related output bypass capacitor
See GNSS receiver hardware integration manual
U2
I2C-bus bidirectional voltage translator
TCA9406DCUR - Texas Instruments
U3
Generic unidirectional voltage translator
SN74AVC2T245 - Texas Instruments
Table 36: Components for connecting SARA-R500S/SARA-R510S modules to a u-blox 3.0 V GNSS receiver