Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 83 of 123
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2.6.5 DDC (I2C) interface
2.6.5.1 Guidelines for DDC (I2C) circuit design
☞ Communication with an external GNSS receiver is not supported by SARA-R510M8S modules.
The DDC I2C-bus master interface can be used to communicate with u-blox GNSS receivers and other
external I2C-bus slaves as an audio codec.
The SDA and SCL pins of the module are open drain output as per I2C bus specifications [9], and they
have internal pull-up resistors to the V_INT 1.8 V supply rail of the module, so there is no need of
additional pull-up resistors on the external application board.
☞ Capacitance and series resistance must be limited on the bus to match the I2C specifications
(1.0 s is the max allowed rise time on SCL and SDA lines): route connections as short as possible.
☞ ESD sensitivity rating of the DDC (I2C) pins is 1 kV (HBM according to JESD22-A114). Higher
protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible points.
☞ If the pins are not used as DDC bus interface, they can be left unconnected.
Connection with u-blox 1.8 V GNSS receivers
Figure 64 shows a circuit example for connecting the cellular module to a u-blox 1.8 V GNSS receiver:
The SDA and SCL pins of the cellular module are directly connected to the related pins of the u-blox
1.8 V GNSS receiver. External pull-up resistors are not needed, as they are already integrated in the
cellular module.
The GPIO2 pin is connected to the active-high enable pin of the voltage regulator that supplies the
u-blox 1.8 V GNSS receiver providing the “GNSS supply enable” function. A pull-down resistor is
provided to avoid a switch on of the positioning receiver when the cellular module is switched off
or in the reset state.
The GPIO3 and GPIO4 pins are directly connected respectively to TXD1 and EXTINT0 pins of the
u-blox 1.8 V GNSS receiver providing “GNSS data ready” and “GNSS RTC sharing” functions.
For additional guidelines regarding the design of applications with u-blox 1.8 V GNSS receivers, see
the hardware integration manuals of the u-blox GNSS receivers.
IN
OUT
GND
GNSS LDO
regulator
SHDN
u-blox GNSS
1.8 V receiver
SDA2
SCL2
VMAIN1V8
U1
23
GPIO2
SDA
SCL
C1
26
27
VCC
R1
GNSS supply enabled
SARA-R500S / SARA-R510S
TXD1
GPIO3
24
GNSS data ready
EXTINT0
GPIO4
25
GNSS RTC sharing
Figure 64: Application circuit for connecting SARA-R500S/SARA-R510S modules to a u-blox 1.8 V GNSS receiver
Reference
Description
Part number - Manufacturer
R1
47 kΩ resistor 0402 5% 0.1 W
Generic manufacturer
U1, C1
Voltage regulator for GNSS receiver and
related output bypass capacitor
See GNSS receiver hardware integration manual
Table 35: Components for connecting SARA-R500S/SARA-R510S modules to a u-blox 1.8 V GNSS receiver