Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 81 of 123
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2.6.2 USB interface
☞ The USB interface is available for diagnostic purpose only.
2.6.2.1 Guidelines for USB circuit design
A suitable application circuit can be similar to the one illustrated in Figure 61, where direct external
access is provided for diagnostic purpose by means of testpoints made available on the application
board for VUSB_DET, USB_D+ and USB_D- lines.
USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as
required by the USB 2.0 specification [4] are part of the module USB pins driver and do not need to be
externally provided.
SARA-R5 series
29
USB_D+
GND
TestPoint
17
VUSB_DET
TestPoint
28
USB_D-
TestPoint
Figure 61: SARA-R5 series modules USB application circuit providing access for diagnostic purpose
☞ The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-
A114F). Higher protection level could be required if the lines are externally accessible and it can be
achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco
Electronics PESD0402-140 ESD protection device) on the lines connected to these pins, close to
accessible points.
☞ It is recommended to provide accessible test points directly connected to the USB interface pins
(VUSB_DET, USB_D+, USB_D-).
2.6.2.2 Guidelines for USB layout design
The characteristic impedance of the USB_D+ / USB_D- lines is specified by the USB 2.0
specification [4]. The most important parameter is the differential characteristic impedance
applicable for the odd-mode electromagnetic field, which should be as close as possible to 90
differential. Signal integrity may be degraded if PCB layout is not optimal, especially when the USB
signaling lines are very long.
Use the following general routing guidelines to minimize signal quality problems:
Route USB_D+ / USB_D- lines as a differential pair
Route USB_D+ / USB_D- lines as short as possible
Ensure the differential characteristic impedance (Z
0
) is as close as possible to 90
Ensure the common mode characteristic impedance (Z
CM
) is as close as possible to 30
Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, whether coupled
differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on
clear PCB area