Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 79 of 123
Confidential
Providing 2 UARTs with the TXD and RXD lines only
☞ Compatible with USIO variants 2/3/4; not compatible with USIO variants 0/1 (see section 1.9.1.1).
If the functionality of the RTS, CTS, DSR and RI lines is not required in the application, or the lines are
not available, then:
Connect the module RTS and DSR input lines to GND or respectively to the CTS and RI output of
the module, since the module requires RTS and DSR active (low electrical level) if HW flow control
is enabled (as it is by default)
If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be
used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard.
If a 1.8 V application processor (DTE) is used, the circuit should be implemented as in Figure 59.
TxD
Application Processor
(1.8V DTE)
RxD
RTS
CTS
TxD
RxD
RTS
CTS
GND
SARA-R5 series
(1.8V DCE)
12
TXD
(TxD1)
9
DTR
(TxD2)
13
RXD
(RxD1)
10
RTS
(RTS1)
11
CTS
(CTS1)
8
DCD
(RxD2)
6
DSR
(RTS2)
7
RI
(CTS2)
GND
0Ω
TP
0Ω
TP
0Ω
TP
TP
UART1
UART2
0Ω
TP
0Ω
TP
0Ω
TP
TP
Figure 59: 2 UART interfaces application circuit with 3-wire links in DTE/DCE serial communications (1.8V DTE)
If a 3.0 V application processor (DTE) is used, then it is recommended to connect the 1.8 V UART
interfaces of the module (DCE) by means of an appropriate unidirectional voltage translator using the
module V_INT output as 1.8 V supply for the voltage translator on the module side, as in Figure 58.
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
RTS
CTS
TxD
RxD
RTS
CTS
GND
SARA-R5 series
(1.8V DCE)
12
TXD
(TxD1)
9
DTR
(TxD2)
13
RXD
(RxD1)
10
RTS
(RTS1)
11
CTS
(CTS1)
8
DCD
(RxD2)
6
DSR
(RTS2)
7
RI
(CTS2)
GND
1V8
B1 A1
U1
B3A3
VCCBVCCA
Unidirectional
voltage translator
C1
C2
3V0
DIR3
DIR1
VCC
B2 A2
B4A4
GND
OE
DIR4
DIR2
0Ω
TP
0Ω
TP
0Ω
TP
TP
TP
0Ω
TP
0Ω
TP
0Ω
TP
TP
UART1
UART2
Figure 60: 2 UART interfaces application circuit with 3-wire links in DTE/DCE serial communications (3.0 V DTE)
Reference
Description
Part number - Manufacturer
C1, C2
100 nF capacitor ceramic X7R 0402 10% 16 V
GCM155R71C104KA55 - Murata
U1
Unidirectional voltage translator
SN74AVC4T774
12
- Texas Instruments
Table 34: Components for 2 UARTs application circuit with 3-wire links in DTE/DCE serial communications (3.0 V DTE)
12
Voltage translator providing partial power down feature, so the 3 V supply can be also ramped up before V_INT 1.8 V supply