Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 74 of 123
Confidential
2.6 Data communication interfaces
2.6.1 UART interfaces
2.6.1.1 Guidelines for UART circuit design
Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
☞ Compatible with USIO variant 1; not compatible with USIO variants 0 / 2 / 3 / 4 (see section 1.9.1.1).
If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim
MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chips
provide the translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V
to RS-232 compatible signal level.
If a 1.8 V application processor (DTE) is used and complete RS-232 functionality is required, then the
complete 1.8 V UART of the module (DCE) should be connected to a 1.8 V DTE, as in Figure 49.
TxD
Application Processor
(1.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
SARA-R5 series
(1.8V DCE)
12
TXD
9
DTR
13
RXD
10
RTS
11
CTS
6
DSR
7
RI
8
DCD
GND
0Ω
TP
0Ω
TP
0Ω
TP
0Ω
TP
Figure 49: 1 UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE)
If a 3.0 V application processor (DTE) is used, then it is recommended to connect the 1.8 V UART of
the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT
output as 1.8 V supply for the voltage translators on the module side, as described in Figure 50.
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
SARA-R5 series
(1.8V DCE)
12
TXD
9
DTR
13
RXD
10
RTS
11
CTS
6
DSR
7
RI
8
DCD
GND
1V8
B1 A1
GND
U1
B3A3
VCCBVCCA
Unidirectional
voltage translator
C1
C2
3V0
DIR3
DIR2 OE
DIR1
VCC
B2 A2
B4A4
DIR4
1V8
B1 A1
GND
U2
B3A3
VCCBVCCA
Unidirectional
voltage translator
C3
C4
3V0
DIR1
DIR3 OE
B2 A2
B4A4
DIR4
DIR2
0Ω
TP
0Ω
TP
0Ω
TP
0Ω
TP
TP
Figure 50: 1 UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)
Reference
Description
Part number - Manufacturer
C1, C2, C3, C4
100 nF capacitor ceramic X7R 0402 10% 16 V
GCM155R71C104KA55 - Murata
U1, U2
Unidirectional voltage translator
SN74AVC4T774
7
- Texas Instruments
Table 29: Components for 1 UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)
7
Voltage translator providing partial power down feature, so the 3 V supply can be also ramped up before V_INT 1.8 V supply