Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 67 of 123
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2.4.4.2 Guidelines for ANT_DET layout design
Figure 44 describes the recommended layout for the cellular antenna detection circuit to be provided
on the application board to achieve antenna detection functionality, implementing the recommended
schematic described in the previous Figure 43 and Table 23:
The ANT pin must be connected to the cellular antenna connector by means of a 50
transmission line, implementing the design guidelines described in section 2.4.2 and the
recommendations of the SMA connector manufacturer.
DC blocking capacitor at ANT pin (C2) must be placed in series to the 50 RF line.
The ANT_DET pin must be connected to the 50 transmission line by means of a sense line.
Choke inductor in series at the ANT_DET pin (L1) must be placed so that one pad is on the 50
transmission line and the other pad represents the start of the sense line to the ANT_DET pin.
The additional components (R1, C1 and D1) on the ANT_DET line must be placed as ESD protection.
The additional high pass filter (C3 and L2) on the ANT line is placed as ESD immunity improvement
SARA module
C2
R1
D1
C1
L1
J1
C3 L2
Figure 44: Suggested layout for antenna detection circuit on application board
2.4.5 Cellular antenna dynamic tuning control interface
SARA-R5 series modules support a wide range of frequencies, from 600 MHz to 2200 MHz. To provide
more efficient antenna designs over a wide bandwidth, I2S_TXD and I2S_WA pins can be configured
to change their output value according to the LTE band used by the module (see sections 1.11 and 2.8).
These pins, paired with an external antenna tuner IC or RF switch, can be used to:
tune antenna impedance to reduce power losses due to mismatch
tune antenna aperture to improve total antenna efficiency
select the optimal antenna for each operating band
Table 24 reports the antenna dynamic tuning pins setting at the related module operating band.
I2S_TXD
I2S_WA
LTE frequency band in use
0
0
B71 ( < 700 MHz )
0
1
B12, B13, B28, B85 ( 700..800 MHz )
1
0
B5, B8, B18, B19, B20, B26 ( 800..900 MHz )
1
1
B1, B2, B3, B4, B25, B66 ( > 1000 MHz )
Table 24: SARA-R5 series modules antenna dynamic tuning truth table