Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 65 of 123
Confidential
2.4.4 Cellular antenna detection interface (ANT_DET)
2.4.4.1 Guidelines for ANT_DET circuit design
Figure 43 and Table 23 describe the recommended schematic / components for the cellular antenna
detection circuit to be provided on the application board and for the diagnostic circuit that must be
provided on the antenna’s assembly to achieve antenna detection functionality.
Application board
Antenna cable
SARA-R5 series
56
ANT
62
ANT_DET
R1
C1 D1
L1
C2
J1
Z
0
= 50
Ω
Z
0
= 50
Ω
Z
0
= 50 ohm
Antenna assembly
R2
C4
L3
Radiating
element
Diagnostic
circuit
GND
L2
C3
Figure 43: Suggested schematic for antenna detection circuit on application PCB and diagnostic circuit on antenna assembly
Reference
Description
Part number - Manufacturer
C1
27 pF capacitor ceramic C0G 0402 5% 50 V
GRM1555C1H270JA16 - Murata
C2
33 pF capacitor ceramic C0G 0402 5% 50 V
GRM1555C1H330JA16 - Murata
D1
Very low capacitance ESD protection
PESD0402-140 - Tyco Electronics
L1
68 nH multilayer inductor 0402 (SRF ~1 GHz)
LQG15HS68NJ02 - Murata
R1
10 k resistor 0402 1% 0.063 W
Generic manufacturer
J1
SMA connector 50 through hole jack
SMA6251A1-3GT50G-50 - Amphenol
C3
15 pF capacitor ceramic C0G 0402 5% 50 V
GRM1555C1H150J - Murata
L2
39 nH multilayer inductor 0402 (SRF ~1 GHz)
LQG15HN39NJ02 - Murata
C4
22 pF capacitor Ceramic C0G 0402 5% 25 V
GCM1555C1H270JA16 - Murata
L3
68 nH multilayer inductor 0402 (SRF ~1 GHz)
LQG15HS68NJ02 - Murata
R2
15 k resistor for diagnostics
Generic manufacturer
Table 23: Suggested parts for antenna detection circuit on application PCB and diagnostic circuit on antennas assembly
The antenna detection and diagnostic circuit suggested in Figure 43 and Table 23 are here explained:
When antenna detection is forced by the +UANTR AT command (see the SARA-R5 series AT
commands manual [1]), the ANT_DET pin generates a DC current measuring the resistance (R2)
from the antenna connector (J1) provided on the application board to GND.
DC blocking capacitors are needed at the ANT pin (C2) and at the antenna radiating element (C4)
to decouple the DC current generated by the ANT_DET pin.
Choke inductors with a Self-Resonance Frequency (SRF) in the range of 1 GHz are needed in series
at the ANT_DET pin (L1) and in series at the diagnostic resistor (L3), to avoid a reduction of the RF
performance of the system, improving the RF isolation of the load resistor.
Resistor on the ANT_DET path (R1) is needed for accurate measurements through the +UANTR
AT command. It also acts as an ESD protection.
Additional components (C1 and D1 in Figure 43) are needed at the ANT_DET pin as ESD protection.
Additional high pass filter (C3 and L2 in Figure 43) is provided as ESD immunity improvement
The ANT pin must be connected to the antenna connector by means of a transmission line with
nominal characteristics impedance as close as possible to 50 .