Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 61 of 123
Confidential
After the antenna detection circuit with the layout illustrated on the left side of Figure 37, the antenna
RF trace is designed as a 50 grounded coplanar waveguide on the bottom layer of the u-blox host
printed circuit board, with total length ~29 mm, with layout and thickness, width, gap (signal to
ground) characteristics illustrated in Figure 38. Guidelines to design a proper equivalent 50
transmission line on a host printed circuit board are available in section 2.4.1.2.
RF trace
Bottom Layer (L4) Layout
35 µm
35 µm
35 µm
35 µm
220 µm
220 µm
1200 µm
L1 copper
L3 copper
L2 copper
L4 copper
FR-4 dielectric
FR-4 dielectric
FR-4 dielectric
PCB stack-up structure
310 µm 500 µm500 µm
L1 C1
D1
Figure 38: 50 grounded coplanar waveguide transmission line designed on the u-blox host PCB bottom layer
The 50 grounded coplanar waveguide routed on the bottom layer is terminated on a dedicated 50
SMA female connector mounted on the top layer, consisting in the cellular RF input/output of the host
PCB for external antenna and/or RF coaxial cable access, with board layout illustrated in Figure 39.
Guidelines to design a proper equivalent 50 termination on a host printed circuit board are available
in section 2.4.1.3, with antenna selection and design guidelines available in section 2.4.2.1.
Top Layer (L1) Layout L2 Layout L3 Layout Bottom Layer (L4) Layout
RF trace
L1-L4 viaL1-L4 via L1-L4 via L1-L4 via
SMA
Figure 39: 50 SMA female connector layout on the u-blox host PCB
The 50 characteristic impedance of the antenna trace design on a host printed circuit board can be
verified using a Vector Network Analyzer, as done on the u-blox host PCB, with calibrated RF coaxial
cable soldered at the pad corresponding to RF input/output of the module and with the transmission
line terminated to a 50 load at the 50 SMA female connector.
Compliance of the design with regulatory rules and specifications defined by the FCC, ISED, RED, etc.
can be verified using a radio communication tester (callbox) as the Rohde & Schwarz CMW500, or any
equivalent equipment for multi-technology signaling conformance tests.