Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 60 of 123
Confidential
The u-blox host printed circuit board has a structure of 4 Copper layers with 35 m thickness (1 oz/ft
2
)
each, using FR4 dielectric substrate material with 4.3 typical permittivity at 1 GHz, and 0.013 typical
loss tangent at 1 GHz.
The top layer layout of the u-blox host PCB designed to accommodate the ANT pad of SARA-R5 series
module is described in Figure 36: the left side illustrates top layer copper mask and top layer solder
resist mask, with top layer to bottom layer vias; the right side illustrates the PCB stack-up structure.
Considering that the thickness of the dielectric material from the top layer to the buried layer is larger
than 200 m, no GND keep-out is implemented on the buried metal layer area below the ANT pad.
Guidelines to design an equivalent proper connection for the ANT pad on a host printed circuit board
are available in section 2.4.1.1.
ANT pad
1.5 x 0.8 mm
400µm
300µm300µm
RF trace
L1-L4 via
Top Layer (L1) Layout
35 µm
35 µm
35 µm
35 µm
220 µm
220 µm
1200 µm
Top Layer (L1) copper
L3 copper
L2 copper
Bottom Layer (L4) copper
FR-4 dielectric
FR-4 dielectric
FR-4 dielectric
PCB stack-up structure
Figure 36: Top layer layout and stack-up structure of the u-blox host PCB for the ANT pad of the module
As illustrated on the left side of Figure 36, the antenna RF trace is routed from the RF pad on the top
layer (L1) to the bottom layer (L4) through a dedicated via. After the via, the antenna RF trace, as 50
transmission line, is connected to the antenna detection circuit described in Figure 35 and Table 20,
with the layout illustrated on the left side of Figure 37. Guidelines to design a proper equivalent
(optional) antenna detection circuit on a host printed circuit board are available in section 2.4.4.
ANT_DET
RF trace
L1-L4 via
Bottom Layer (L4) Layout
35 µm
35 µm
35 µm
35 µm
220 µm
220 µm
1200 µm
L1 copper
L3 copper
L2 copper
L4 copper
FR-4 dielectric
FR-4 dielectric
FR-4 dielectric
PCB stack-up structure
C2
L1
C1
D1
R1
RF trace
Figure 37: Bottom layer layout and stack-up structure of the u-blox host PCB for the antenna detection circuit