Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 59 of 123
Confidential
2.4.2.3 Antenna trace design used for SARA-R5 series modules’ type approvals
The conformity assessment of u-blox SARA-R5 series LGA surface-mounted modules for regulatory
type approvals such as FCC United States, ISED Canada, RED Europe, etc. has been carried out with
the SARA-R5 series modules mounted on a u-blox host printed circuit board with a 50 grounded
coplanar waveguide designed on it, herein referenced as “antenna trace design”, implementing the
connection of the ANT LGA pad of the module, consisting in the cellular RF input/output of the
module, up to a dedicated 50 SMA female connector, consisting in the cellular RF input/output of
the host printed circuit board for external antenna and/or RF cable access.
☞ Manufacturers of mobile or fixed devices incorporating SARA-R5 series modules are authorized to
use the FCC United States Grants and ISED Canada Certificates of SARA-R5 series modules for
their own final host products if, as per FCC KDB 996369, the antenna trace design implemented
on the host PCB is electrically equivalent to the antenna trace design implemented on the u-blox
host PCB used for regulatory type approvals of SARA-R5 series modules, described in this section.
☞ In case of antenna trace design change, an FCC Class II Permissive Change and/or ISED Class IV
Permissive Change application is required to be filed by the grantee, or the host manufacturer can
take responsibility through the change in FCC ID and/or the ISES Multiple Listing (new application)
procedure followed by an FCC C2PC and/or ISED C4PC application.
The antenna trace design is implemented on the u-blox host PCB as illustrated in Figure 35, using the
parts listed in Table 20, with the support of the additional optional antenna detection capability.
Guidelines to design a proper equivalent optional antenna detection circuit on a host printed circuit
board are available in section 2.4.4.
u-blox host PCB
SARA-R5 series
56
ANT
62
ANT_DET
R1
C1 D1
L1
C2
J1
Z
0
= 50
Ω
Z
0
= 50
Ω
GND
L2
Figure 35: Antenna trace design implemented on the u-blox host PCB, with additional antenna detection circuit
Reference
Description
Part number - Manufacturer
C1
27 pF capacitor ceramic C0G 0402 5% 50 V
GRM1555C1H270JA16 - Murata
C2
33 pF capacitor ceramic C0G 0402 5% 50 V
GRM1555C1H330JA16 - Murata
D1
Very low capacitance ESD protection
PESD0402-140 - Tyco Electronics
L1
68 nH multilayer inductor 0402 (SRF ~1 GHz)
LQG15HS68NJ02 - Murata
R1
10 k resistor 0402 1% 0.063 W
Generic manufacturer
J1
SMA connector 50 through hole jack
SMA6251A1-3GT50G-50 - Amphenol
L2
39 nH multilayer inductor 0402 (SRF ~1 GHz)
Not Installed
Table 20: Parts in use on the u-blox host PCB for the antenna trace design, with additional antenna detection circuit