Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 55 of 123
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2.4.1.3 Guidelines for RF termination design
☞ The GNSS antenna RF interface is not supported by SARA-R500S and SARA-R510S modules.
The RF termination must provide a characteristic impedance of 50 as well as the RF transmission
line up to the RF termination, to match the characteristic impedance of ANT and ANT_GNSS ports.
However, real antennas do not have a perfect 50 load on all the supported frequency bands. So to
reduce as much as possible any performance degradation due to antenna mismatching, the RF
termination must provide optimal return loss (or VSWR) figures over all the operating frequencies, as
summarized in Table 6 and Table 7.
If an external antenna is used, the antenna connector represents the RF termination on the PCB:
Use a suitable 50 connector providing a clean PCB-to-RF-cable transition.
Strictly follow the connector manufacturer’s recommended layout, for example:
o SMA Pin-Through-Hole connectors require a GND keep-out (i.e. clearance, a void area) on all
the layers around the central pin up to the annular pads of the four GND posts, as illustrated in
Figure 33 or in Figure 39.
o U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in
the area below the connector between the GND land pads, as illustrated in 34.
Figure 34: U.FL surface mounted connector mounting pattern layout
Cut out the GND layer under the RF connector and close to any buried vias, to remove stray
capacitance and thus keep the RF line at 50 , e.g. the active pad of U.FL connector needs to have
a GND keep-out (i.e. clearance, a void area) at least on the first inner layer to reduce parasitic
capacitance to ground.
If an integrated antenna is used, the integrated antenna represents the RF terminations. The
following guidelines should be followed:
Use an antenna designed by an antenna manufacturer providing the best possible return loss.
Provide a ground plane large enough according to the relative integrated antenna requirements.
The ground plane of the application PCB can be reduced down to a minimum size that must be
similar to one quarter of wavelength of the minimum frequency that needs to be radiated. As
numerical example,
Frequency = 617 MHz Wavelength 48 cm Minimum GND plane size 12 cm
It is highly recommended to strictly follow the detailed and specific guidelines provided by the
antenna manufacturer regarding correct installation and deployment of the antenna system,
including the PCB layout and matching circuitry.
Further to the custom PCB and product restrictions, the antenna may require a tuning to comply
with all the applicable required certification schemes. It is recommended to consult the antenna
manufacturer for antenna matching design-in guidelines relative to the custom application.
Additionally, these recommendations regarding the antenna system placement must be followed:
Do not place the antennas within a closed metal case.
Do not place the cellular antenna in close vicinity to the end user since the emitted radiation in
human tissue is restricted by regulatory requirements.
Place the antennas as far as possible from VCC supply line and related parts (see also Figure 27),
from high speed digital lines (as USB) and from any possible noise source.