Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 54 of 123
Confidential
If the distance between the transmission line and the adjacent GND area (on the same layer) does not
exceed 5 times the width of the line, use the “Coplanar Waveguide” model for the 50 calculation.
Additionally to the 50 impedance, the following guidelines are recommended for transmission lines:
Minimize the transmission line length: the insertion loss should be minimized as much as possible,
in the order of a few tenths of a dB,
Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component
present on the RF transmission lines, if top-layer to buried layer dielectric thickness is below
200 m, to reduce parasitic capacitance to ground,
The transmission lines width and spacing to GND must be uniform and routed as smoothly as
possible: avoid abrupt changes of width and spacing to GND,
Add GND stitching vias around transmission lines, as described in Figure 33,
Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground
layer, providing enough vias on the adjacent metal layer, as described in Figure 33,
Route RF transmission lines far from any noise source (as switching supplies and digital lines) and
from any sensitive circuit (as USB),
Avoid stubs on the transmission lines,
Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried
metal layer,
Do not route microstrip lines below discrete component or other mechanics placed on top layer
Two examples of a suitable RF circuit design for ANT pin are illustrated in Figure 33, where the cellular
antenna detection circuit is not implemented (if the cellular antenna detection function is required by
the application, follow the guidelines for circuit and layout implementation detailed in section 2.4.4):
In the first example shown on the left, the ANT pin is directly connected to an SMA connector by
means of a suitable 50 transmission line, designed with the appropriate layout.
In the second example shown on the right, the ANT pin is connected to an SMA connector by
means of a suitable 50 transmission line, designed with the appropriate layout, with an
additional high pass filter to improve the ESD immunity at the antenna port. (The filter consists
of a suitable series capacitor and shunt inductor, for example the Murata GRM1555C1H150JB01
15 pF capacitor and the Murata LQG15HN39NJ02 39 nH inductor with SRF ~1 GHz.).
SARA module
SMA
connector
SARA module
SMA
connector
High-pass filter
to improve
ESD immunity
Figure 33: Example of circuit and layout for ANT RF circuits on the application board
☞ Refer to section 2.4.2.3 for the description of the antenna trace design implemented on the u-blox
host printed circuit board used for conformity assessment of SARA-R5 series surface-mounted
modules for regulatory type approvals such as FCC United States, ISED Canada, RED Europe, etc.