Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 52 of 123
Confidential
2.4 Antenna interfaces
SARA-R5 series modules provide a cellular RF interface for connecting the external cellular antenna:
the ANT pin represents the cellular RF input/output for cellular signals transmission and reception.
SARA-R510M8S modules provide also a GNSS RF interface for connecting the external GNSS
antenna: the ANT_GNSS pin represents the GNSS RF input for GNSS signals reception.
The ANT and ANT_GNSS pins have a nominal characteristic impedance of 50 and must be
connected to the related physical antenna through a 50 transmission line to allow clean
transmission / reception of RF signals.
2.4.1 General guidelines for antenna interfaces
2.4.1.1 Guidelines for ANT and ANT_GNSS pins RF connection design
☞ The GNSS antenna RF interface is not supported by SARA-R500S and SARA-R510S modules.
A clean transition between the ANT and ANT_GNSS pads and the application board PCB must be
provided, implementing the following design-in guidelines for the layout of the application PCB close
to the ANT and ANT_GNSS pads:
On a multilayer board, the whole layer stack below the RF connections should be free of digital lines
Increase GND keep-out (i.e. clearance, a void area) around the ANT and ANT_GNSS pads, on the
top layer of the application PCB, to at least 250 m up to adjacent pads metal definition and up to
400 m on the area below the module, to reduce parasitic capacitance to ground, as described in
the left picture in Figure 30
Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT and
ANT_GNSS pads if the top-layer to buried layer dielectric thickness is below 200 m, to reduce
parasitic capacitance to ground, as described in the right picture in Figure 30
Min.
250 µm
Min. 400 µm
GND
RF pad
GND clearance
on buried layer very close to top layer
below RF pad
GND clearance
on top layer
around RF pad
Figure 30: GND keep-out area on top layer around RF pad and on very close buried layer below RF pad (ANT / ANT_GNSS)
☞ Refer to section 2.4.2.3 for the description of the antenna trace design implemented on the u-blox
host printed circuit board used for conformity assessment of SARA-R5 series surface-mounted
modules for regulatory type approvals such as FCC United States, ISED Canada, RED Europe, etc.