Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 51 of 123
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2.3.2 Module reset (RESET_N)
2.3.2.1 Guidelines for RESET_N circuit design
SARA-R5 series RESET_N is equipped with an internal active pull-up; an external pull-up resistor is
not required and should not be provided.
If connecting the RESET_N input to a push button, the pin will be externally accessible on the
application device. According to EMC/ESD requirements of the application, an additional ESD
protection device (e.g. the EPCOS CA05P4S14THSG varistor) should be provided close to accessible
point on the line connected to this pin, as described in Figure 29 and Table 16.
☞ ESD sensitivity rating of the RESET_N pin is 1 kV (HBM according to JESD22-A114). Higher
protection level can be required if the line is externally accessible on the application board, e.g. if
an accessible push button is directly connected to the RESET_N pin, and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point.
An open drain output or open collector output is suitable to drive the RESET_N input from an
application processor, as described in Figure 29.
☞ RESET_N input pin should not be driven high by an external device, as it may cause start up issues.
SARA-R5 series
18
RESET_N
Push button
ESD
Open
drain
output
Application
Processor
SARA-R5 series
18
RESET_N
TP
TP
Figure 29: RESET_N application circuits using a push button and an open drain output of an application processor
Reference
Description
Part number - Manufacturer
ESD
Varistor for ESD protection
B72590T8140S160 - TDK
Table 16: Example of ESD protection component for the RESET_N application circuits
☞ If the external reset function is not required by the customer application, the RESET_N input pin
can be left unconnected to external components, but it is recommended providing direct access
on the application board by means of an accessible test point directly connected to the RESET_N
pin.
2.3.2.2 Guidelines for RESET_N layout design
The RESET_N circuit require careful layout due to the pin function (see section 1.6.3). Ensure that the
voltage level is well defined during operation and no transient noise is coupled on this line, otherwise
the module might detect a spurious reset request. It is recommended to keep the connection line to
RESET_N pin as short as possible.