Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 41 of 123
Confidential
Figure 21 and the components listed in Table 10 show an example of a power supply circuit for
SARA-R5 series modules, where the module VCC is supplied by an LDO linear regulator capable of
delivering maximum peak / pulse current specified for LTE use-case, with suitable power handling
capability.
It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly
below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V for the VCC, as in the
circuits described in Figure 21 and Table 10). This reduces the power on the linear regulator and
improves the thermal design of the circuit.
5V
C1
R1
IN OUT
ADJ
GND
5
8
1
3
4
C2
R2
R3
U1
EN
SARA-R5 series
52
VCC
53
VCC
51
VCC
GND
C4
C3
C5 C6
Figure 21: Example of VCC supply circuit for SARA-R5 series modules, using an LDO linear regulator
Reference
Description
Part number - Manufacturer
C1
1 F capacitor ceramic X5R 6.3 V
Generic manufacturer
C2
22 F capacitor ceramic X5R 25 V
Generic manufacturer
C3
100 nF capacitor ceramic X7R 16 V
GCM155R71C104KA55 - Murata
C4
10 nF capacitor ceramic X7R 16 V
GRT155R71C103KE01 - Murata
C5
68 pF capacitor ceramic C0G 0402 5% 50 V
GRM1555C1E680JA01 - Murata
C6
15 pF capacitor ceramic C0G 0402 5% 50 V
GJM1555C1H150JB01 - Murata
R1
47 k resistor 0.1 W
Generic manufacturer
R2
41 k resistor 0.1 W
Generic manufacturer
R3
10 k resistor 0.1 W
Generic manufacturer
U1
LDO linear regulator 1.0 A
AP7361C – Diodes Incorporated
Table 10: Components for VCC supply circuit for SARA-R5 series modules, using an LDO linear regulator
☞ See the section 2.2.1.9, and in particular Figure 26 / Table 14, for the parts recommended to be
provided if the application device integrates an internal antenna.
2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following
prerequisites to comply with the module VCC requirements summarized in Table 5:
Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output
circuit connected to the VCC pins must be capable of delivering the maximum current occurring
during a transmission at maximum Tx power, as specified in SARA-R5 series data sheet [1]. The
maximum discharge current is not always reported in the data sheets of batteries, but the
maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours
divided by 1 hour.
DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of
avoiding a VCC voltage drop below the operating range summarized in Table 5 during
transmission.