Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 40 of 123
Confidential
SARA-R5 series
12V
C2C1
VCC
EN
PG
VSW
GND
8
9 1
4
2
D1
L1
U1
BST
FB
5
R1
R2
52
VCC
53
VCC
51
VCC
GND
3V8
C6 C7 C8
PGND
C4
C3
C5
11
10
C9
Figure 20: Example of VCC supply circuit for SARA-R5 series modules, using a step-down regulator
Reference
Description
Part number - Manufacturer
C1
10 F capacitor ceramic X7R 50 V
Generic manufacturer
C2
10 nF capacitor ceramic X7R 16 V
Generic manufacturer
C3
22 nF capacitor ceramic X7R 16 V
Generic manufacturer
C4
22 F capacitor ceramic X5R 25 V
Generic manufacturer
C5
22 F capacitor ceramic X5R 25 V
Generic manufacturer
C6
100 nF capacitor ceramic X7R 16 V
GCM155R71C104KA55 - Murata
C7
10 nF capacitor ceramic X7R 16 V
GRT155R71C103KE01 - Murata
C8
68 pF capacitor ceramic C0G 0402 5% 50 V
GRM1555C1E680JA01 - Murata
C9
15 pF capacitor ceramic C0G 0402 5% 50 V
GJM1555C1H150JB01 - Murata
D1
Schottky diode 30 V 2 A
MBR230LSFT1G - ON Semiconductor
L1
4.7 H inductor 20% 2 A
SLF7045T-4R7M2R0-PF - TDK
R1
470 k resistor 0.1 W
Generic manufacturer
R2
150 k resistor 0.1 W
Generic manufacturer
U1
Step-down regulator 1 A 1 MHz
TS30041 - Semtech
Table 9: Components for the VCC supply circuit for SARA-R5 series modules, using a step-down regulator
☞ See the section 2.2.1.9, and in particular Figure 26 / Table 14, for the parts recommended to be
provided if the application device integrates an internal antenna.
2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
The use of a linear regulator is suggested when the difference from the available supply rail source
and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to
a voltage value within the module VCC normal operating range.
The characteristics of the Low Drop-Out (LDO) linear regulator connected to VCC pins should meet
the following prerequisites to comply with the module VCC requirements summarized in Table 5:
Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a
voltage value to the VCC pins within the specified operating range and must be capable of
delivering to VCC pins the maximum current consumption occurring during a transmission at the
maximum Tx power, as specified in the SARA-R5 series data sheet [1].
Power dissipation: the power handling capability of the LDO linear regulator must be checked to
limit its junction temperature to the rated range (i.e. check the voltage drop from the maximum
input voltage to the minimum output voltage to evaluate the power dissipation of the regulator).