Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Design-in Page 37 of 123
Confidential
2 Design-in
2.1 Overview
For an optimal integration of the SARA-R5 series modules in the final application board, follow the
design guidelines stated in this section.
Every application circuit must be suitably designed to guarantee the correct functionality of the
relative interface, but a number of points require particular attention during the design of the
application device.
The following list provides a rank of importance in the application design, starting from the highest
relevance:
1. Module antennas connection: ANT, ANT_GNSS
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and ANT_DET pins.
Antenna circuit directly affects the RF compliance of the device integrating a SARA-R5 series
module with applicable certification schemes. Follow the suggestions provided in the relative
section 2.4 for schematic and layout design.
2. Module supply: VCC and GND pins.
The supply circuit affects the RF compliance of the device integrating a SARA-R5 series module
with the applicable required certification schemes as well as the antenna circuits design. Very
carefully follow the suggestions provided in the relative section 2.2.1 for schematic and layout
design.
3. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST pins.
Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling.
Carefully follow the suggestions provided in relative section 2.5 for schematic and layout design.
4. System functions: PWR_ON and RESET_N pins.
Accurate design is required to guarantee that the voltage level is well defined during operation.
Carefully follow the suggestions provided in relative section 2.3 for schematic and layout design.
5. Other digital interfaces: UART, USB, SPI, SDIO, I2C, I2S and GPIOs.
Accurate design is required to guarantee correct functionality and reduce the risk of digital data
frequency harmonics coupling. Follow the suggestions provided in sections 2.6, 2.7 and 2.8 for
schematic and layout design.
6. Other supplies: V_INT generic digital interfaces supply.
Accurate design is required to guarantee correct functionality. Follow the suggestions provided in
the corresponding section 2.2.2 for schematic and layout design.
☞ It is recommended to follow the specific design guidelines provided by each manufacturer of any
external part selected for the application board integrating the u-blox cellular modules.
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Not supported by SARA-R500S and SARA-R510S modules