Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 System description Page 33 of 123
Confidential
The following lines are provided:
data lines (DCD as data output, DTR as data input)
hardware flow control lines (RI as flow control output, DSR as flow control input)
o Ring indication function over the GPIO pin configured for this purpose (see section 1.11)
o DTR function, to control low power idle mode in case of +UPSV: 3 setting, over the GPIO pin
configured for this purpose (see section 1.11)
UART general features, valid for all variants, are:
Serial port with RS-232 functionality conforming to the ITU-T V.24 recommendation [5], with
CMOS compatible levels (0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state)
Hardware flow control (default value) or none flow control are supported
UART power saving indication available on the hardware flow control output, if hardware flow
control is enabled: the line is driven to the OFF state when the module is not prepared to accept
data by the UART interface
One-shot autobauding is supported and it is enabled by default: automatic baud rate detection is
performed only once, at module start up. After the detection, the module works at the fixed baud
rate (the detected one) and the baud rate can be changed via AT command
The default frame format is 8N1 (8 data bits, no parity, 1 stop bit)
SARA-R5 series modules are designed to operate as cellular modems, i.e. as the data
circuit-terminating equipment (DCE) according to the ITU-T V.24 recommendation [5]. A host
application processor connected to the module UART interface represents the data terminal
equipment (DTE).
☞ UART signal names of the cellular modules conform to the ITU-T V.24 recommendation [5]:
e.g. TXD line represents data transmitted by the DTE (host processor output) and received by the
DCE (module input).
SARA-R5 series modules’ UART interface is by default configured for AT commands: the module
waits for AT command instructions and interprets all the characters received as commands to
execute. All the functionalities supported by SARA-R5 series modules can be in general set and
configured by AT commands:
AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8]
u-blox AT commands (see the SARA-R5 series AT commands manual [2])
The UART interfaces settings can be suitably configured by AT commands (for more details, see the
SARA-R5 series AT commands manual [2]).
Figure 18 describes the 8N1 frame format.
D0 D1 D2 D3 D4 D5 D6 D7
Start of 1-Byte
transfer
Start Bit
(Always 0)
Possible Start of
next transfer
Stop Bit
(Always 1)
t
bit
= 1/(Baudrate)
Normal Transfer, 8N1
Figure 18: Description of UART default frame format (8N1 = 8 data bits, no parity, 1 stop bit), with fixed baud rate