Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 System description Page 24 of 123
Confidential
1.6.2 Module power-off
1.6.2.1 Switch-off events
SARA-R5 series modules can be gracefully switched off, triggering the storage of the current
parameter settings in the non-volatile memory of the module and performing a clean network detach
procedure, by:
+CPWROFF AT command (see SARA-R5 series AT commands manual [2]).
Forcing a low pulse on the PWR_ON pin (normally high due to internal pull-up) for a valid time
period (see the SARA-R5 series data sheet [1]).
A fast emergency shutdown procedure of the modules, without storage of the current parameter
settings in the module’s non-volatile memory and without proper network detach, can be triggered by:
Toggling the GPIO input pin configured with fast emergency shutdown function (see section 1.11)
An abrupt under-voltage shutdown occurs on SARA-R5 series modules when the VCC supply is
removed. If this occurs, it is not possible to perform the storing of the current parameter settings in
the module’s non-volatile memory or to perform the proper network detach.
☞ It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R5 series
modules normal operations.
1.6.2.2 Switch-off sequence by +CPWROFF AT command
Figure 14 describes the switch-off sequence of the modules started by the +CPWROFF AT command,
allowing storage of parameter settings in the non-volatile memory and a clean network detach:
When the +CPWROFF AT command is sent the module starts the switch-off routine.
Then the module replies OK on the AT interface: the switch-off routine is in progress.
At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage
regulators are turned off, including the generic digital interfaces supply (V_INT).
Then, the module remains in switch-off mode as long as a switch-on event does not occur
(e.g. applying a low level to PWR_ON), or enters not-powered mode if the VCC supply is removed.
VCC
PWR_ON
RESET_N
V_INT
Internal reset
System state
BB pads state Operational
OFF
Tristate / Floating
ON
Operational →
Tristate
AT+CPWROFF
sent to the module
0 s
~2.5 s
~5 s
OK
replied by the module
VCC can be
removed
Figure 14: SARA-R5 series modules switch-off sequence by means of +CPWROFF AT command
☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor
the V_INT pin to sense the end of the switch-off sequence.
☞ The duration of each phase in the SARA-R5 series modules’ switch-off routines can largely vary,
depending on the application / network settings and the concurrent module activities.