Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 System description Page 23 of 123
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1.6.1.3 Switch-on / wake-up sequence from power-off / deep-sleep mode
Figure 13 shows the SARA-R5 series modules switch-on or wake-up sequence from the power-off or
deep-sleep mode:
The external power supply is still applied to the VCC module pins, with the module being previously
switched off (by means of the +CPWROFF AT command or by proper PWR_ON pin toggling), or
with the module being previously entered deep-sleep mode.
The PWR_ON pin is held low for a valid time, representing the start-up event.
All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT).
The internal reset signal is held low: the baseband core and all digital pins are held in reset state.
When the internal reset signal is released, any digital pin is set in the correct sequence from the
reset state to the default operational configured state. The duration of this phase differs within
generic digital interfaces and USB interface due to host / device enumeration timings.
If enabled, a greeting message is sent on the RXD pin (for more details, see SARA-R5 series AT
commands manual [2])
The module is fully ready to operate after all interfaces are configured.
VCC
PWR_ON
RESET_N
V_INT
Internal reset
RXD
System state
BB pads state Operational
OFF
Tristate / Floating
Internal reset
Internal reset → Operational
ON
Start of interface
configuration
Module interfaces
are configured
Start-up
event
~? s
0 s
Greeting
Figure 13: SARA-R5 series switch-on / wake-up sequence description from power-off / deep-sleep mode
1.6.1.4 General considerations for the switch-on procedure
If the greeting text is not used by the external application to detect that the module is ready to reply
to AT commands, then the only way of checking it is polling: the external application can start sending
“AT” after that the CTS line is set to the ON state (in case UART is used as AT interface with HW flow
control enabled as default), but any AT command sent before the time when the module is ready to
reply may be not buffered and may be lost.
☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor:
o the V_INT pin, to sense the start of the SARA-R5 series module switch-on sequence
o the GPIO pin configured to provide the module status indication or module operating mode
indication (see SARA-R5 series AT commands manual [2], +UGPIOC), to sense when the
module is ready to operate
☞ Before the switch-on of the generic digital interface supply (V_INT) of the module, no voltage
driven by an external application should be applied to any generic digital interface of the module.
☞ The duration of the SARA-R5 series modules’ switch-on routine can vary depending on the
application / network settings and the concurrent module activities.