Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 System description Page 19 of 123
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1.5.1.4 VCC current consumption in low power idle mode
(low power mode enabled)
The low power mode configuration is by default disabled, but it can be enabled using the +UPSV AT
command (see the SARA-R5 series AT commands manual [2]).
When low power mode is enabled, the module automatically enters the low power idle mode whenever
possible, but it must periodically monitor the paging channel of the current base station (paging block
reception), in accordance to the 2G / LTE system requirements, even if connected mode is not enabled
by the application. When the module monitors the paging channel, it wakes up to the active mode to
enable the reception of the paging block. In between, the module switches to low power mode. This is
known as discontinuous reception (DRX) or extended discontinuous reception (eDRX).
1.5.1.5 VCC current consumption in active mode
(low power mode and PSM disabled)
The active mode is the state where the module is switched on and ready to communicate with an
external device by means of the application interfaces (as the UART serial interface). The module
processor core is active and the 26 MHz reference clock frequency is used.
If low power mode configuration is disabled, as it is by default (see the SARA-R5 series AT commands
manual [2], +UPSV AT commands for details), the module remains in active mode. Otherwise, if low
power mode configuration is enabled, the module enters low power idle mode (and deep-sleep mode
power saving mode, if enabled) whenever possible.
Figure 8 shows a typical example of the module current consumption profile when the module is in
active mode. Here, the module is registered with the network and, while active mode is maintained,
the receiver is periodically activated to monitor the paging channel for paging block reception.
ACTIVE MODE
Paging period
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
enabled
0
100
0
100
Figure 8: VCC current consumption profile with low power mode disabled and module registered with the network: active
mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception