Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 System description Page 14 of 123
Confidential
Function
Pin Name
Pin No
I/O
Description
Remarks
Audio
I2S_TXD
35
O
I2S transmit data
I2S transmit data. Not supported by “00” product version.
Alternatively configurable by +UGPIOC AT command.
I2S_RXD
37
I
I2S receive data
I2S receive data. Not supported by “00” product version.
I2S_CLK
36
I/O
I2S clock
I2S clock. Not supported by “00” product version.
I2S_WA
34
I/O
I2S word
alignment
I2S word alignment. Not supported by “00” product version.
Alternatively configurable by +UGPIOC AT command.
GPIO
GPIO1
16
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO2
23
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO /
Time stamp
output
4
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO5
42
I/O
Pin for SIM card
detection
See sections 1.8.2 and 1.11 for functional description.
See sections 2.5 and 2.8 for external circuit design-in.
GPIO6
19
I/O
GPIO /
Time pulse output
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
I2S_TXD
35
O
Pin for antenna
dynamic tuning
Configurable as output for antenna dynamic tuning.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
I2S_WA
34
O
Pin for antenna
dynamic tuning
Configurable as output for antenna dynamic tuning.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
EXT_INT
33
I
External interrupt
Configurable as interrupt input triggering the generation of an
URC time stamp.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
SDIO_CMD
46
I
External time
pulse input
4
Configurable as input for external GNSS time pulse.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
Reserved
RSVD
2
N/A
Reserved pin
Leave unconnected.
See sections 1.12 and 2.9.
Table 3: SARA-R5 series modules pin definition, grouped by function
4
Not supported by SARA-R510M8S modules