Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 System description Page 13 of 123
Confidential
Function
Pin Name
Pin No
I/O
Description
Remarks
USB
VUSB_DET
17
I
USB detect input
VBUS USB supply generated by the host must be connected
to this input pin to enable the USB interface.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
Provide test point for diagnostic purposes.
USB_D-
28
I/O
USB Data Line D-
USB interface for diagnostics.
90 nominal differential impedance.
Pull-up, pull-down and series resistors, as required by the USB
2.0 specification [4], are part of the USB pin driver and shall
not be provided externally.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
Provide test point for diagnostic purposes.
USB_D+
29
I/O
USB Data Line D+
USB interface for diagnostics.
90 nominal differential impedance.
Pull-up, pull-down and series resistors, as required by the USB
2.0 specification [4], are part of the USB pin driver and shall
not be provided externally.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
Provide test point for diagnostic purposes.
SPI
SDIO_D0
47
I/O
SPI MOSI
SPI Master Output Slave Input, alternatively settable as SDIO.
Not supported by “00” product version, except for diagnostics.
SDIO_D1
49
I/O
SPI MISO
SPI Master Input Slave Output, alternatively settable as SDIO
Not supported by “00” product version, except for diagnostics.
SDIO_D2
44
I/O
SPI clock
SPI clock, alternatively configurable as SDIO.
Not supported by “00” product version, except for diagnostics.
SDIO_D3
48
I/O
SPI Chip Select
SPI Chip Select, alternatively configurable as SDIO.
Not supported by “00” product version, except for diagnostics.
SDIO
SDIO_D0
47
I/O
SDIO serial
data [0]
SDIO serial data [0], alternatively configurable as SPI MOSI.
Not supported by “00” product version.
SDIO_D1
49
I/O
SDIO serial
data [1]
SDIO serial data [1], alternatively configurable as SPI MISO.
Not supported by “00” product version.
SDIO_D2
44
I/O
SDIO serial
data [2]
SDIO serial data [2], alternatively configurable as SPI clock.
Not supported by “00” product version.
SDIO_D3
48
I/O
SDIO serial
data [3]
SDIO serial data [3], alternatively settable as SPI Chip Select.
Not supported by “00” product version.
SDIO_CLK
45
O
SDIO serial clock
SDIO serial clock.
Not supported by “00” product version.
SDIO_CMD
46
I/O
SDIO command
SDIO command, alternatively configurable by AT+UGPIOC.
Not supported by “00” product version.
DDC
SCL
27
O
I2C bus clock line
Fixed open drain, for communication with I2C-slave devices.
Internal active pull-up: external pull-up is not required.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDA
26
I/O
I2C bus data line
Fixed open drain, for communication with I2C-slave devices.
Internal active pull-up: external pull-up is not required.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.