Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 System description Page 12 of 123
Confidential
Function
Pin Name
Pin No
I/O
Description
Remarks
UART
RXD
13
O
UART data output
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 104 (RxD) in ITU-T V.24, for AT, data,
Mux, FOAT, FW update via u-blox EasyFlash tool.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
12
I
UART data input
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 103 (TxD) in ITU-T V.24, for AT, data,
Mux, FOAT, FW update via u-blox EasyFlash tool.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
11
O
UART clear to
send output
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10
I
UART request to
send input
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR
6
O/I
UART data set
ready output /
AUX UART
request to send
input
USIO variant 0:
Pin disabled
USIO variant 1:
Primary UART circuit 107 (DSR) in ITU-T V.24.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI
7
O
UART ring
indicator output /
AUX UART clear to
send output
USIO variants 0 / 1:
Primary UART circuit 125 (RI) in ITU-T V.24.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DTR
9
I
UART data
terminal ready
input /
AUX UART data
input
USIO variants 0 / 1:
Primary UART circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up enabled.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 103 (TxD) in ITU-T V.24, for AT, data,
GNSS tunneling, FOAT, diagnostics.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DCD
8
O
UART data carrier
detect output /
AUX UART data
output
USIO variant 0:
Pin disabled.
USIO variant 1:
Primary UART circuit 109 (DCD) in ITU-T V.24.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 104 (RxD) in ITU-T V.24, for AT, data,
GNSS tunneling, FOAT, diagnostics.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.