Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Appendix Page 117 of 123
Confidential
Supply source 3V6
GND
330µF
10nF
100nF
56pF
SARA
52
VCC
53 VCC
51 VCC
+
15pF
33RSVD / ADC1 / EXT_INT
0Ω or
ferrite bead
56ANT
62
ANT_DET
10k 68nH
33pF
Connector
27pF
ESD
Cellular
antenna
15pF
39nH
33pF
SIM card
connector
CCVCC (C1)
CCVPP (C6)
CCIO (C7)
CCCLK (C3)
CCRST (C2)
GND (C5)
33pF 33pF 1µF
41
VSIM
39SIM_IO
38SIM_CLK
40SIM_RST
33pF
SW1
SW2
4
V_INT
42RSVD / GPIO5 / SIM_DET
470k
ESD ESD ESD ESD ESD ESD
1k
TP
V_INT
36
RSVD / SPI_CLK / I2S_CLK
34
RSVD / SPI_MOSI / I2S_WA
35
RSVD / SPI_CS / I2S_TXD
37
RSVD / SPI_MISO / I2S_RXD
SDA
SCL
GPIO2 / GPIO3
RSVD / GPIO4
26
27
24
25
RSVD / GPIO2 23
31
RSVD / ANT_GNSS
49
RSVD / SDIO_D1 / MIC_P
48
RSVD / SDIO_D3 / MIC_N
46
RSVD / SDIO_CMD / MIC_BIAS
47
RSVD / SDIO_D0 / MIC_GND
44
RSVD / SDIO_D2 / SPK_P
45
RSVD / SDIO_CLK / SPK_N
3V6
16GPIO1
Network
indicator
TP
TXD
RXD
RTS
CTS
RI
GND
UART DTE
Application
processor
12 TXD
7
RI / RSVD
13 RXD
10 RTS
11 CTS
8
DCD / RSVD
6
DSR / RSVD
9
DTR / RSVD
GND
29 USB_D+ / TXD_FT / TXD_AUX / RSVD
28
USB_D- / RXD_FT / RXD_AUX / RSVD
TP
TP
17
VUSB_DET / USB_5V0 / TXD_AUX / RSVD
TP
0Ω
21 GND / VSEL
0Ω
0Ω
0Ω
19
GPIO6 / RXD_AUX / CODEC_CLK / RSVD
2
V_BCKP / USB_3V3 / RSVD
18
RESET_N / PWR_OFF
15 PWR_ON / RSVD
100k
TP
TP
GPIO
GPIO
VCC
Supply source 3V0
Supply source 2V8
Supply source 1V8
0Ω
0Ω
0Ω
0Ω
0Ω
59
GND / ANT_BT
GPIO
LEGEND
Mount for SARA-N2 only
Mount for SARA-G3/-U2 only
Mount for all modules
Mount for all modules except SARA-N2/-N3/-G4
Mount for all modules except SARA-G4/-N3
Mount for all modules except SARA-N2
Mount for SARA-N3 only
Mount for SARA-G4 only
Mount for SARA-R422M8S/-R510M8S only
GNSS
antenna
0Ω
TP
TP
Mount for all modules except SARA-R42x
SAW
LNA
Figure 75: Example schematic to integrate a SARA-R4, SARA-R5, SARA-N2, SARA-N3, SARA-G3, SARA-G4 and/or SARA-U2 module in the same application PCB, using main interfaces