Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Appendix Page 112 of 123
Confidential
No
SARA-R41x
SARA-R42x
SARA-R5xx
SARA-N2xx
SARA-N3xx
SARA-G3xx
SARA-G4xx
SARA-U2xx
26
SDA
SDA
SDA
SDA
SDA
SDA
SDA
SDA
I2C data
16
V_INT level (1.8 V)
Open drain
Internal pull-up: 2.2 kΩ
I2C data
V_INT level (1.8 V)
Open drain
Internal pull-up: 2.2 kΩ
I2C data
V_INT level (1.8 V)
Open drain
Internal active pull-up
I2C data
15
V_INT level (1.8 V)
Open drain
No internal pull-up
I2C data
14
V_INT level (1.8 / 2.8 V)
Open drain
Internal pull-up: 10 kΩ
I2C data
V_INT level (1.8 V)
Open drain
No internal pull-up
I2C data
14
V_INT level (1.8 / 3.0 V)
Open drain
No internal pull-up
I2C data / AUX UART input
V_INT level (1.8 V)
Open drain
No internal pull-up
27
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
I2C clock
17
V_INT level (1.8 V)
Open drain
Internal pull-up: 2.2 kΩ
I2C clock
V_INT level (1.8 V)
Open drain
Internal pull-up: 2.2 kΩ
I2C clock
V_INT level (1.8 V)
Open drain
Internal active pull-up
I2C clock
15
V_INT level (1.8 V)
Open drain
No internal pull-up
I2C clock
V_INT level (1.8 / 2.8 V)
Open drain
Internal pull-up: 10 kΩ
I2C clock
V_INT level (1.8 V)
Open drain
No internal pull-up
I2C clock
14
V_INT level (1.8 / 3.0 V)
Open drain
No internal pull-up
I2C clock / AUX UART out
V_INT level (1.8 V)
Open drain
No internal pull-up
28
USB_D-
USB_D-
USB_D-
RSVD
RXD_FT
RXD_AUX
RXD_FT
USB_D-
USB data I/O (D-)
High-speed USB 2.0
TestPoint recommended
USB data I/O (D-)
High-speed USB 2.0, only
for FW update / diagnostic
TestPoint recommended
USB data I/O (D-)
High-speed USB 2.0
TestPoint recommended
Reserved
FW update & Trace output
V_INT level (1.8 / 2.8 V)
Driver strength: 3 mA
TestPoint recommended
AUX UART data output
V_INT level (1.8 V)
Driver strength: 5 mA
TestPoint recommended
FW update & Trace output
V_INT level (1.8 / 3.0 V)
Driver strength: 3 mA
TestPoint recommended
USB data I/O (D-)
High-speed USB 2.0
TestPoint recommended
29
USB_D+
USB_D+
USB_D+
RSVD
TXD_FT
TXD_AUX
TXD_FT
USB_D+
USB data I/O (D+)
High-speed USB 2.0
TestPoint recommended
USB data I/O (D+)
High-speed USB 2.0, only
for FW update / diagnostic
TestPoint recommended
USB data I/O (D+)
High-speed USB 2.0
TestPoint recommended
Reserved
FW update & Trace input
V_INT level (1.8 / 2.8 V)
Internal pull-up: ~171 kΩ
TestPoint recommended
AUX UART data input
V_INT level (1.8 V)
Internal pull-up:~18 kΩ
TestPoint recommended
FW update & Trace input
V_INT level (1.8 / 3.0 V)
Internal pull-up: ~166 kΩ
TestPoint recommended
USB data I/O (D+)
High-speed USB 2.0
TestPoint recommended
30
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
31
RSVD
ANT_GNSS
ANT_GNSS
RSVD
RSVD
RSVD
RSVD
RSVD
Reserved
GNSS RF input
18
GNSS RF input
18
Reserved
Reserved
Reserved
Reserved
Reserved
32
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
33
RSVD
RSVD
EXT_INT
RSVD
ADC1
RSVD
RSVD
RSVD
Reserved
It can be grounded
Reserved
TestPoint recommended
External interrupt
It can be grounded
Reserved
It can be grounded
ADC input
It can be grounded
Reserved
It must be grounded
Reserved
It can be grounded
Reserved
It must be grounded
34
I2S_WA / SPI_MOSI
I2S_WA
I2S_WA
RSVD
RSVD
I2S_WA
I2S_WA
I2S_WA
I2S W.A.
19
/ SPI MOSI
19
V_INT level (1.8 V)
Driver strength: 2 mA
I2S Word Alignment
20
V_INT level (1.8 V)
Driver strength: 2 mA
I2S Word Alignment
20
V_INT level (1.8 V)
Configurable as Antenna
Dynamic Tuner
Reserved
Reserved
I2S Word Alignment
V_INT level (1.8 V)
Driver strength: 6 mA
I2S Word Alignment
14
V_INT level (1.8 V / 3.0 V)
I2S Word Alignment / GPIO
V_INT level (1.8 V)
Driver strength: 2 mA
35
I2S_TXD / SPI_CS
I2S_TXD
I2S_TXD
RSVD
RSVD
I2S_TXD
I2S_TXD
I2S_TXD
I2S out
19
/ SPI CS
19
V_INT level (1.8 V)
Driver strength: 2 mA
I2S data output
20
V_INT level (1.8 V)
Driver strength: 2 mA
I2S data output
20
V_INT level (1.8 V)
Configurable as Antenna
Dynamic Tuner
Reserved
Reserved
I2S data output
V_INT level (1.8 V)
Driver strength: 5 mA
I2S data output
14
V_INT level (1.8 V / 3.0 V)
I2S data output / GPIO
V_INT level (1.8 V)
Driver strength: 2 mA
16
Not supported by ‘00’ and ‘01’ product versions
17
Not supported by ‘00’ and ‘01’ product versions
18
Not supported by SARA-R422, SARA-R422S, SARA-R500S, SARA-R510S
19
Not supported by ‘00’, ‘01’, ‘x2’ and ‘x3’ product versions
20
Not supported by ‘00’ product version